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Careers

Job ID FPGAD01
Job FPGA/RTL Designer
Job Profile
  1. RTL programming (Verilog/System Verilog)
  2. FPGA Design Development
  3. Working with FPGA Development Tool (Quartus, Modelsim, Xilinx ISE, Libero etc..)
  4. Functional and timing simulation using Verilog/System Verilog
  5. RTL Code Optimization to meet timing closure and fit on-chip resources
  6. Support all phases of FPGA base product development
  7. System Architecture Design
  8. Testing and troubleshooting of hardware
Department Systems Hardware
Type Full time permanent position
Vacancies 1
Location V.U.Nagar, Gujarat, India.
Education
  • BE/B.Tech in Electronics/Electronics & Communication from recognized university with good academic Record
  • ME/M.Tech in Electronics/VLSI Design from recognized university with good academic Record
Skill(s)
  • Knowledge of
    • Experience with SystemVerilog/Verilog for design and verification
    • In-depth understanding of FPGA design flow/methodology, IP integration and design collateral
    • Should be able to develop the small blocks of IP from scratch and do basic functional verification
    • Knowledge of scripting language like Pearl/Python/TCL
    • Knowledge of USB, Ethernet, PCIe and external memories such as DDR and QDR RAM
    • Should be familiar with protocols like SPI, I2C and UART
    • Understanding of standard/specification/application for IP design or system design
    • Must be an effective and efficient communicator. Capable of doing oral and written communication in English
    • Self-motivated to learn and to contribute. Ability to work effectively with global teams
Additional Skill(s)
  • Knowledge of Altera Quartus II Tool, Questasim, Modelsim
  • Knowledge of Xilinx tool like ISE, Vivado
  • Knowledge of Microsemi tool like libero
Experience Minimum 2 years of Experience in Semiconductor field
Application Guidelines Candidate must send their application with Subject "[FPGAD01] Job Application".
Application without JOB ID would not be considered.
Apply This email address is being protected from spambots. You need JavaScript enabled to view it.
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