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eUSB 3.1 Gen 2 Device Controller (eUSB31SF)

Model No. IPRUSB3SFP005

Rating: Not Rated Yet
Description

 

 

Leveraging the benefits of eUSB 3.0/3.1 Gen 1 device controller, eUSB 3.1 Gen 2 is designed using the Intel FPGA built-in 10 Gbps transceiver. It is a one-stop solution for all USB requirements ranging from USB 3.1 to USB 2.0. It supports SuperSpeed+ (SSP), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes. The Core architecture allows to use minimal pins from FPGA for USB 3.1 interface with better stability. It provides USB 2.0 backward compatibility using an external USB 2.0 ULPI PHY.

It has been designed to provide simplicity and flexibility along with highest throughput i.e. >7Gbps. Avalon interface allows to manage the control transfer using software, provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.

Block Diagram:

Performance Results:

U31Gen2 Read Speed 500 opt         U31Gen2 Write Speed 500 opt

 

Features:

  • USB 3.1 Specific Features
    • Supports SuperSpeedPlus (SSP - USB 3.1 Gen 2) mode and ports SuperSpeed (SS - USB3.1 Gen 1) mode
    • Uses Intel Transceiver as a PHY layer and thus eliminates need for external PHY for USB 3.1
  • USB 2.0 Specific Features
    • Supports High Speed (HS) and Full Speed (FS) modes
    • Provides well-known ULPI interface to interact with external USB 2.0 PHY
  • Ease of Use
    • Ready to use component for Intel’s Qsys
    • Simple FIFO interface to transfer data over non-control endpoint
  • Flexibility
    • Capable to support up to 31 endpoints (1 default control endpoint, 15 IN endpoints and 15 OUT endpoints)
    • Allows to select number of buffers per endpoint based on the requirement

Implementation Results:

Supported FamilyResource UtilizationMemory Blocks
Cyclone 10 (up to Gen 2 10Gbps Interface)~17902 ALM~74 M20K
Arria 10 (up to Gen 2 10Gbps Interface)~16948 ALM~74 M20K
Cyclone V (up to Gen 1 5Gbps Interface)~6210 ALM~71 M10K
Arria V (up to Gen 1 5Gbps Interface)~6190 ALM~74 M10K

Note:

  • Results are based on 1-Bulk IN and 1-Bulk OUT endpoint with 16K buffer each.

Deliverables:

ContentsEvaluation LicenseFull Development License
License Type One (1) month evaluation license at no cost
Note: License can be extended for another month after examining request (Evaluation Now)
Encrypted IP Core Perpetual license for development
Note: Other licensing schemes and source code are also available
Reference Design Included for Altera Arria 10 Development Board and FMC eUSB 3.1 Snap On Board Included for Included for Altera Arria 10 Development Board and FMC eUSB 3.1 Snap On Board
Demonstration
  • Enumeration Demo
  • Mass Storage Demo
  • UVC Demo
  • Loopback Test Demo
  • Enumeration Demo
  • Mass Storage Demo
  • UVC Demo
  • Loopback Test Demo
Nios II Sample Applications (with C code) Enumeration Enumeration
Encrypted IP Core design files with Control, 1-Bulk IN and 1-Bulk OUT endpoints Yes Yes
Drivers Windows Reference Drivers (object code) Windows Reference Drivers (object code)
Software Library (Compiled version)
  • VC++
  • VC++
Technical Documents
  • IP Core User Guide
  • Windows API User Guide
  • IP Core User Guide
  • Windows API User Guide
Programming files generation support Time-limited (4 hours) Full programming
Technical Support Pre sales support from support team 1 Year integration support for Intel Quartus

 

Application:

  • Imaging Device
  • Storage Devices
  • Machine Vision
  • Data Centers

Support:

  • IP integration support is available with the purchase of full version
  • Additional support on chargeable basis for a period of 3 months or more
  • IP Core modification support available at additional cost Licensing

Licensing:

  • OpenCore Plus Evaluation : 1 month evaluation license at free of cost
  • Full : Project based Perpetual License
  • Renewal : To continue support and getting future updates after a year of purchasing IP core, license renewal is available at nominal fees

Downloads:

Related Links:

 

 

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