The USB 1.1 Device IP core is a universal serial bus (USB) function controller that provides a USB full-speed function interface and meets USB 1.1 Specification. This IP core is available with 3 standard endpoints (1 CTRL, 1 BULK IN, 1 Bulk OUT ) configuration with maximum payload size. Each endpoint requires a FIFO to be associated with it. The FIFO size for the Endpoint 0 is fixed at 64 bytes and for Bulk IN and OUT is fixed at 128bytes (64x2 bytes).

The core has been optimized for the popular FPGA devices and its functionality has been verified on the real hardware. It is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.

Block Diagram:

• Verilog Implementation on RTL level
• Supports full-speed devices
• The core will perform all USB enumeration in harware
• All interfaces are architected using a FIFO based model
• Physical Layer Interface (UTMI compliant)
• Avalon Interconnection compliant
• Extraction clock and data signals in internal digital phase-locked loop (DPLL)
• Cyclic redundancy code (CRC) checking/generation
• Data toggle synchronization mechanism
• Optimized for use with Altera Nios embedded processor

Example LE Usage

Verification

• USB 1.1 Device core's functionality is verified in Model-Sim simulation software using test bench written in Verilog HDL.
• USB 1.1 IP is also tested by interfacing with USB 1.1 PHY chip on SLS ESDK Board.

• Evaluation version
  • Encrypted Core
  • One (1) month evaluation license at no cost (from the License Request page )
  • Reference Design with time limited SOF for ESDK 1C12 Education Kit (QAR file)
  • Nios II Sample Application
    • Port Interface
  • Drivers
    • HAL Driver (Source Code)
    • Windows Driver (Compiled Version)
  • Software Library (Compiled Version)
    • VC ++
    • C# .net
  • Documentation
    • IP Core user guide
    • Design from scratch tutorial
    • HAL Driver API
    • Windows Driver API
  • Utilities
    • Port Interface
    • USB View
    • Enumeration Data Editor
• Full version
  • Encrypted Core
  • One (1) year development license for single project on single node. Other licensing schemes available. Please contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it for details
  • Reference Design with full programming file generation for CoreCommander development board
  • Nios II Sample Application
    • Port Interface
  • Drivers
    • HAL Driver (Source Code)
    • Windows Driver (Compiled Version)
  • Software Library (Compiled Version)
    • VC ++
    • C# .net
  • Documentation
    • IP Core user guide
    • Design from scratch tutorial
    • HAL Driver API
    • Windows Driver API
  • Utilities
    • Port Interface
    • USB View
    • Enumeration Data Editor
• View the Eval and Full version comparison of the IP core Deliverables.

• Embedded microcontroller systems
• Communication systems

• USB 1.1 IP Core Brochure
• USB 1.1 IP Core Documents