The USB 1.1 Device, Software Based Enumeration IP Core is RAM based USB 1.1 device core with 32-bit Avalon interface. The core supports Full Speed (12 Mbps) functionality and Low Speed (1.5 Mbps) functionality can be added as per customer request with additional charges. The core supports three preconfigured Control, Bulk IN and Bulk OUT endpoints. It can be configurable for up to 15 IN/OUT endpoints on customer request on chargeable basis. Each configurable endpoints has an endpoint controller that supports Interrupt, Bulk and Isochronous transfers.
The core has been optimized for Altera FPGAs and its functionality has been verified on the hardware with Altera Quartus II. The package includes ModelSim precompiled library for core simulation and verification.
Verilog Implementation on RTL level
Supports Full-speed (12 Mbps) transfer rate
Software based USB enumeration Support
Avalon Interconnection compliant
Preconfigured for 3 endpoints
Configurable for up to 15 IN/OUT endpoints which supports Bulk,Isochronous and Interrupt functionality on customer request at additional cost
Cyclic redundancy code (CRC) checking/generation
Data toggle synchronization mechanism
Optimized for use with Altera NiosII embedded processor
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