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MOD_BT_PHONE

USB 1.1 Device, Software Based Enumeration (USB11SR)

Model No. IPRUSB1SFP002

Rating: Not Rated Yet
Description

 

 

The USB 1.1 Device, Software Based Enumeration IP Core is RAM based USB 1.1 device core with 32-bit Avalon interface. The core supports Full Speed (12 Mbps) functionality and Low Speed (1.5 Mbps) functionality can be added as per customer request with additional charges. The core supports three preconfigured Control, Bulk IN and Bulk OUT endpoints. It can be configurable for up to 15 IN/OUT endpoints on customer request on chargeable basis. Each configurable endpoints has an endpoint controller that supports Interrupt, Bulk and Isochronous transfers.

The core has been optimized for Altera FPGAs and its functionality has been verified on the hardware with Altera Quartus II. The package includes ModelSim precompiled library for core simulation and verification.

Block Diagram:

Features:

  • Verilog Implementation on RTL level
  • Supports Full-speed (12 Mbps) transfer rate
  • Software based USB enumeration Support
  • Avalon Interconnection compliant
  • Preconfigured for 3 endpoints
    • CONTROL
    • BULK IN
    • BULK OUT
  • Configurable for up to 15 IN/OUT endpoints which supports Bulk,Isochronous and Interrupt functionality on customer request at additional cost
  • Cyclic redundancy code (CRC) checking/generation
  • Data toggle synchronization mechanism
  • Optimized for use with Altera NiosII embedded processor

Notes : (1) USB 1.1 Device IP Core with FIFO interface (USB11HF) is available on request at additional cost.Please contact support@slscorp.com
              (2) The Low Speed functionality is available on customer request at additional charges.

Implementation Results:

Supported FamilyResource UtilizationMemory BlocksPerformance ( ULPI Clock - fmax )
Cyclone III1900 LE8 M9K103MHz
Cyclone IV1900 LE8 M9K109MHz
Cyclone V840 ALM8 M10K60MHz
Stratix III1300 ALUT8 M9K141MHz
Stratix IV1300 ALUT8 M9K130MHz
Stratix V800 ALM8 M20K100MHz
Arria II1300 ALUT8 M9K115MHz
Arria V830 ALM8 M10K83MHz
MAX 101900 LE8 M9K104MHz

Note: The implementation results may change upon core revision

Verification:

  • USB11SR Device core's functionality is verified in ModelSim simulation software using test bench written in Verilog HDL
  • USB11SR IP is also tested by interfacing with USB 1.1 PHY chip on SLS ESDK 1C12 Board

Deliverables:

ContentsEvaluation LicenseFull Development License
License Type One (1) month evaluation license at no cost
Note: License can be extended for another month after examining request (Evaluation Now)
Encrypted IP Core Perpetual license for development
Note: Other licensing schemes and source code are also available
Reference Design Included for ESDK 1C12 Board Included for ESDK 1C12 Board
Demonstration Mass Storage, Port Interface, Performance Test (Streaming Bulk IN and Bulk OUT), CDC Serial Mass Storage, Port Interface, Performance Test (Streaming Bulk IN and Bulk OUT), CDC Serial
Nios II Sample Applications Port Interface, Streaming Port Interface, Streaming
Drivers
  • Windows Reference Drivers (object code)
  • HAL Driver (Source Code)
  • Windows Reference Drivers (object code)
  • HAL Driver (Source Code)
Software Library (Compiled version)
  • VC++
  • VC++
Utilities USB View and Port Interface USB View and Port Interface
Technical Documents
  • IP Core User Guide
  • Hardware and Simulation Tutorial
  • Window API User Guide
  • HAL Driver API User Guide
  • IP Core User Guide
  • Hardware and Simulation Tutorial
  • Window API User Guide
  • HAL Driver API User Guide
Technical Support Pre sales support from support team 1 Year integration support for Altera Quartus II

Downloads:

 

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