The USB 2.0 Device with FIFO Interface (USB20HF) IP Core supports ULPI interface with Bulk IN and Bulk OUT endpoints. The core supports three preconfigured endpoints Control, Bulk IN, and Bulk OUT. It is Configurable for up to 15 IN/OUT endpoints on customer request on chargeable basis¹. Each configurable endpoint has an endpoint controller that supports Interrupt, Bulk, and Isochronous transfers. The USB 2.0 Device IP communicates with the Host through FIFO interface. The core supports both High Speed (480 Mbps) and full Speed (12 Mbps) functionality.

The core has been optimized for Altera FPGAs and its functionality has been verified on the hardware with Altera Quartus II. The package includes ModelSim pre-compiled library for core simulation and verification.

Benefits

• Complete solution comprising of core, software and board for easy and quick implementation
• Reduced risk with proven, compliant technology
• Premier direct support from SLS IP designers
• Low system and license cost
• Software drivers included

Block Diagram:

• USB2.0USBIF high-speed certified (TID# 70710071)
• Supports both Full Speed (12Mbps) and High Speed (480Mbps) USB operation
• Supported Interfaces²
  • ULPI (NXP ISP1504 PHY)
• FIFO Based USB 2.0 Device IP Core
• Preconfigured for 3 endpoints
  • CONTROL
  • BULK IN
  • BULK OUT
• Configurable for up to 15 endpoints including Isochronous and Interrupt on customer request at additional cost
• Hardware Based USB Enumeration
• Optimized LE count
• Implemented in verilog RTL

Ready to use development kit and snap on boards (supporting santa cruz expansion header) available now!

Example LE Usage

Please Note: The numbers can change upon core revision. Please contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it for latest figures

Verification

• USB20HF IP core's functionality is verified in ModelSim simulation software using test bench written in Verilog RTL

• Evaluation version  
  • Encrypted Core
  • One (1) month evaluation license at no cost (from the License Request page )
  • Demonstrations
    • USB Read/Write
  • Reference Design with time limited SOF for CoreCommander development board(QAR file)
  • Simulation library for Modelsim version 6.3g
  • Utilities
    • Enumeration data editor
    • USBView
  • Software Drivers
    • Windows and Linux reference drivers (object code)
  • Documentation
    • IP Core user guide
    • Design from scratch tutorial
• Full version
  • CoreCommander Development Board
  • Encrypted Core
  • Perpetual license for single project on single node. Other licensing schemes available. Please contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it for details
  • Demonstrations
    • USB Read/Write
  • Reference Design with full programming file generation support for CoreCommander development board
  • Simulation library for Modelsim version 6.3g
  • Utilities
    • Enumeration data editor
    • USBView
  • Software Drivers
    • Windows and Linux reference drivers (object code)
  • Documentation
    • IP Core user guide
    • Design from scratch tutorial
• View the Eval and Full version comparison of the IP core Deliverables.

• USB20HF IP Core Brochure
• USB20HF IP Core Documents
• Reference Designs