The USB20SR is a USB 2.0 USB IF high-speed certified device IP Core. The core is RAM based with 32-bit Avalon interface and supports ULPI interface and Software Enumeration. It supports both High Speed (480 Mbps) and Full Speed (12 Mbps) functionality alongwith three preconfigured endpoints Control, IN, and OUT. It can be configurable up to 15 IN/OUT endpoints on customer request on chargeable basis. Each configurable endpoint has an endpoint controller that supports interrupt, bulk, and isochronous transfers.

The core has been optimized for Altera FPGAs and its functionality has been verified on the hardware with Altera Quartus II. The package includes ModelSim precompiled library for core simulation and verification.

Actual Performance Data

(For ULPI Ram based solution)

Benefits

• Complete solution comprising of core, software and board for easy and quick implementation
• Reduced risk with proven, compliant technology
• Premier direct support from SLS IP designers
• Low system and license cost
• Software drivers included
• Ready to use peripheral for Nios^® II applications

Block Diagram:

Features

• USB 2.0 USB IF high-speed certified (TID# 70680007)
• Supports both High Speed (480 Mbps) and Full Speed (12 Mbps)
• High speed or Full speed operation selection through Software
• ULPI Interface support
• Preconfigured for 3 endpoints
  • CONTROL
  • IN
  • OUT
• Configurable for up to 15 IN/OUT endpoints which supports Bulk, Isochronous and Interrupt functionality on each endpoint on customer request at additional cost
• Software controlled CONTROL, IN, and OUT endpoints
• Optimized for use with Altera Nios II embedded processor
• Avalon System Interconnect Fabric compliant
• Optimized LE count

Implementation Results

Please Note: The numbers can change upon core revision. Please contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it for latest figures

Verification

• USB20SR IP core is tested on the CoreCommander board.
• USB20SR IP core's functionality is verified in ModelSim simulation software using test bench written in Verilog HDL.

• Evaluation version  
  • Encrypted Core
  • One (1) month evaluation license at no cost (from the License Request page )
  • Demonstrations
    • Mass Storage
    • Port Interface
    • HID Mouse Interface
    • Performance Test (Streaming Bulk IN and Bulk OUT)
  • Reference Design with time limited SOF for CoreCommander development board(QAR file)
  • Simulation library for Altera Modelsim
  • Software Drivers
    • HAL driver (object code)
    • Windows reference driver (object code)
  • Software library (VC)
  • Nios II Sample Application (with C code)
    • Port Interface
    • Streaming
  • Documentation
    • IP Core user guide
    • Nios II HAL API User Guide
    • Winodws API User Guide
    • Hardware and Simulation tutorial
  • Utilities
    • USBView
    • Port Interface
• Full version
  • CoreCommander Board
  • Encrypted Core
  • Perpetual license for single project on single node. Other licensing schemes available. Please contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it for details
  • Demonstrations:
    • Mass Storage
    • Port Interface
    • HID Mouse Interface
    • Performance Test (Streaming Bulk IN and Bulk OUT)
  • Reference Design with full programming file generation support for CoreCommander development board (QAR file)
  • Simulation library for Altera Modelsim
  • Software Drivers
    • HAL driver (object code)
    • Windows reference driver (object code)
  • Software library (VC)
  • Nios II Sample Applications (with C code)
    • Port Interface
    • Streaming
  • Documentation
    • IP Core user guide
    • Nios II HAL API User Guide
    • Winodws API User Guide
    • Hardware and Simulation tutorial
  • Utilities
    • USBView
    • Port Interface
• View the Eval and Full version comparison of the IP core Deliverables.

Application Example : MASS STORAGE

• USB20SR IP Core Brochure
• USB20SR IP Core Documents