The SLS USB 3.0 Device core is the SuperSpeed core that supports connectivity between TI USB3.0 Phy (TUSB1310 ) and Altera FPGA. The Core is wrapped around with software drivers and examples for its ease of use and quick integration. The ready to use development board availability makes the integration faster. The core package also contains the reference design that can be used directly for starting a custom application development.

The core has been optimized for Altera FPGAs and its functionality has been verified on the hardware with Altera Quartus II. The package includes ModelSim precompiled library for core simulation and verification.

Development Board

Cyclone IV E FPGA Texas USB1310 PHY USB 2.0 to UART Port 2x128 MB DDR2 SDRAM 5x8 Gbit NAND FLASH 64 Mbit SDR SDRAM 64 Mbit CFI Flash HSMC Connector µSD Card Reader GPIO Headers 4xPush Button Switches and 4xLEDs

Actual Performance Data:

Although the SLS USB 3.0 core is designed and proven working at maximum throughput in a point to point environment, in reality the overall systsem determines the real speed implementation would experience.

Notice: All Host Controllers are not cerated equally!!!

Block Diagram:

Features

• Implementation of Link Layer & Protocol Layer
• Support 16-bit and 32-bit Phy layer data interface
• Supports CONTROL, BULK transfer without stream support
• USB2.0 backward compatible
• All Link layer power state handling
• Implements CRC calculation and generation in hardware
• Configurable end-point selection

Implementation Results

Verification

• USB 3.0 Device IP core's functionality is verified in ModelSim simulation software using test bench written in Verilog HDL.

• Evaluation version
  • OpenCore Plus Evaluation
  • One (1) month evaluation license at no cost
  • Time-limited (4 hours) SOF generation support
  • Reference design for SLS USB 3.0 Development Board
    • SOPC based
    • Qsys based
  • Demonstrations
    • USB Enumeration
    • USB Mass Storage Device Class
    • YUV2 Camera
  • Simulation library for Altera Modelsim version
  • Nios II Sample Applications (with C code)
    • Enumeration
  • Documentation
    • IP Core user guide
    • Windows API User Guide
  • Windows Reference Driver (Object Code)
  • Software Library
    • VC++
  • Utilities
    • USB View
    • Amcap
• Full version
  • Encrypted Core
  • Perpetual license with full version purchase for single project and single site. Other licensing schemes also available.
  • Reference design for SLS USB 3.0 Development Board
    • SOPC based
    • Qsys based
  • Demonstrations
    • USB Enumeration
    • USB Mass Storage Device Class
    • YUV2 Camera
  • Full programming files generation support
  • Simulation library for Altera Modelsim version
  • Nios II Sample Applications (with C code)
    • Enumeration
  • Documentation
    • IP Core user guide
    • Windows API User Guide
  • Windows Reference Driver (Object Code)
  • Software Library
    • VC++
  • Utilities
    • USB View
    • Amcap

• USB 3.0 Device (USB30SF) IP Core Brochure
• USB 3.0 Device (USB30SF) IP Core Documents