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Graphics LCD Controller

Model No. IPR0LCDSFP001
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Graphics LCD Controller
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Graphics LCD Controller supports LCD display with user programmable resolutions and video timings, thus providing capability with almost all available LCD displays. The core supports number of color modes including 32bpp, 24bpp, 16bpp, and 8bpp (Grayscale). The core can interrupt the host on each horizontal and/or vertical sync pulse.

The core has been optimized for popular FPGA devices and its functionality has been verified on the hardware. It is provided as Altera Quartus II Mega function (Altera SOPC Builder ready component) and can be integrated easily into any SOPC Builder generated system using Nios® II Avalon bus.

 

Block Diagram:

Features

  • Separate Vertical Sync/Horizontal Sync and combined Composite Sync signals, Also composite BLANK signal
  • User programmable video timing
  • User programmable video resolution
  • User programmable video control signal polarization levels
  • 32bpp, 24bpp, 16bpp, and 8bpp (GrayScale) color modes
  • Operation from a wide range of input clock frequency
  • Static synchronous design
  • Fully Synthesizable

 

Example Of LE Usage

Targeted Family LEs Memory Bits Performance (Fmax)
Cyclone III 1246 4480 160 MHz

 

Verification

  • Graphics LCD Controller IP core's functionality is verified on NEEK Kit(Cyclone III 3C25) board.

  • Embedded systems
  • PDA

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