The VGA/LCD Controller IP is a synthesizable core which integrates a VGA display controller compatible with VGA/SVGA standards.The VGA/LCD Controller supports CRT and TFT LCD Displays with user programmable resolutions and video timings.The core supports number of color modes, including 32bpp, 24bpp, 16bpp, 8bpp (Grayscale & Pseudo-color) for backdrop layer. In addition to this, it supports 2 layers, 32bpp and 16bpp with alpha and two hardware cursor supports with 64x64 and 32x32 modes. The video memory is located outside the primary core, thus it is possible to provide the most flexible memory solution. The memory can be located on-chip or off-chip, shared with the system’s main memory or be dedicated to the VGA system. The core can interrupt the host on each horizontal and/or vertical sync pulse. The horizontal, vertical and composite synchronization polarization level, as well as the blanking polarization level is programmed by software

is provided as Altera Quartus II Mega Function (Altera SOPC Builder ready component) and integrates easily into any SOPC Builder generated system using Avalon Bus.

Features

• CRT and LCD support
• Separate Vertical Sync, Horizontal Sync, combined Composite Sync and composite BLANK signals
• VGA/SVGA VESA standards
• User programmable video timing
• User programmable video resolution
• User programmable video control signal polarization levels
• 32bpp, 24bpp, 16bpp, 8bpp(GrayScale) color mode
• 32bpp layer with layer alpha and pixel alpha
• 16bpp layer with layer alpha
• Two hardware cursor with 2 modes 32x32 and 64x64 pixels
• 3D (alpha blending) support for hardware cursors
• Color lookup table for 8bpp pseudo color mode and 64x64 pixel hardware cursors
• Interface to all standard VGA DAC
• Operation from a wide range of input clock frequency
• Static synchronous design
• Fully Synthesizable

Example Of LE Usage

Verification

• VGA/LCD Controller IP core is tested on DE2 Kit (Cyclone II 2C35).

• Evaluation version
  • Encrypted Core
  • One (1) month evaluation license at no cost (from the License Request page )
  • Reference Design with time-limited SOF for DE2 Kit (Cyclone II 2C35) (QAR file)
  • Nios II Sample Application
    • Alpha-blending Display
  • Documentation
    • IP Core user guide
    • Design from scratch tutorial
  • Utilities
    • BMP2RAW (MS-Windows)
• Full version
  • Encrypted Core
  • One (1) year development license for single project on single node. Other licensing schemes available. Please contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it for details
  • Reference Design with full programming file generation support for DE2 Kit (QAR file)
  • Nios II Sample Application
    • Alpha-blending Display
  • Documentation
    • IP Core user guide
    • Design from scratch tutorial
  • Utilities
    • BMP2RAW (MS-Windows)
• View the Eval and full version comparison of the IP core Deliverables.

Application Example :  Interface of VGA Controller IP with NIOS II, External Memory & VGA Adapter

• VGA/LCD Controller Brochure
• VGA/LCD Controller Documents