|
Easily build interconnection and expansion interfaces for your SoC design with industry standard IP Cores from SLS.
As a solution to System On a Programmable Chip, SLS provides following set of standard bus interfaces.
| Interface Core |
Description |
Supported Devices |
I²C Controller |
- Avalon interconnect compliant
- Byte by byte data transfers is driven by interrupt or bit polling
- Arbitration-lost interrupt with automatic transfer cancellation
- Bus-busy detection
- Static synchronous design
- Implementation in verilog RTL
|
MAX® II, Cyclone, Cyclone II, Stratix, Stratix II, Stratix GX |
I²C Master |
- Phillips I²C specification version 1.0 compliant
- Clock synchronization, arbitration, multi-master systems and fast speed transmission mode
- Software programmable clock frequency and acknowledgment bit
- Static synchronous design
|
MAX® II, Cyclone, Cyclone II, Stratix, Stratix II, Stratix GX |
I²C Slave |
- Compatible with Phillips I²C Standard
- Supports Normal and Fast Speed
- 7 Addressing modes support
- Static synchronous design
|
MAX II, Cyclone, Cyclone II, Stratix, Stratix II, Stratix GX |
I²S Controller |
- Phillips Inter IC Sound (I²S) specification compliant
- Supports variable data width and sampling frequency between 4KHz to 96KHz
- Provides selection for Master/Slave mode
|
MAX II, Cyclone, Cyclone II, Stratix, Stratix II, Stratix GX |
AC’97 Controller |
- Avalon Bus Compliant
- Compliant with AC’97 Revision 2.1(LM4550)
- Variable and Fixed Sample Rate Support, upto 48 KHz
|
MAX II, Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II, Stratix GX |
|
