I²C (Inter-Integrated Circuit) Controller is a two-wire, bi-directional serial bus that provides simple and efficient method of data transmission over a short distance between many devices. Avalon compliant I²C Controller provides an interface between Nios II processor and I²C device. It can work as Master/Slave transmitter or Master/Slave receiver depending on working mode determined by Nios II processor. The I²C Controller IP core incorporates all features required by the latest I²C specification including clock synchronization, arbitration, multi-master systems and Fast-speed transmission mode.

It is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.

Block Diagram:

Features

• Compatible with Philips I²C(PCF 8584) standard
• Supports both Master and Slave mode
• Automatic detection and adoption to bus interface type
• Multi-master operation
• Byte-by-byte data-transfer is driven by Interrupt or Bit-polling
• Arbitration-lost interrupt with automatic transfer cancellation
• Start/Stop/Repeated Start/Acknowledge generation
• Start/Stop/Repeated Start detection
• Bus-Busy detection
• Supports 7 bit addressing mode
• Operates from wide range of input clock frequencies
• Static synchronous design
• Avalon Bus compliant

Example LE Usage

Verification

• The SLS I²C Controller IP Core's functionality is verified in ModelSim simulation software using test bench written in verilog HDL.
• The I²C Controller's functionality (as a Master) is tested by interfacing with RTC (Real Time Clock) and I²C EPROM on SLS UP3 Education Kit.
• The I²C Controller's functionality (as a Slave) is tested by communicating with another instance of the same core working as master and also with the SLS I²C Master IP Core on the UP3 Education Kit.

• Evaluation version
  • Encrypted Core
  • One (1) month evaluation license at no cost (from the License Request page )
  • Reference Design with full programming file generation for ESDK 1C6 board (QAR file)
  • Simulation library for Altera-Modelsim v6.3g_p1
  • Nios II Sample Application
    • I²C Controller application using Interrupt
    • RTC application using Interrupt
  • Drivers
    • HAL driver (Object code)
  • Documentation
    • IP Core user guide
    • Hardware and Simulation tutorial
    • HAL API user guide
• Full version
  • Encrypted Core
  • Perpetual license for single project on single node. Other licensing schemes available. Please contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it for details
  • Reference Design with full programming file generation for ESDK 1C6 board (QAR file)
  • Simulation library for Altera-Modelsim v6.3g_p1
  • Nios II Sample Application
    • I²C Controller application using Interrupt
    • RTC application using Interrupt
  • Drivers
    • HAL driver (Object code)
  • Documentation
    • IP Core user guide
    • Hardware and Simulation tutorial
    • HAL API user guide
• View the Eval and full version comparison of the IP core Deliverables.

• Embedded microcontroller systems
• Communication systems which includes I²C devices, such as EEPROM memories, temperature sensors, A/D converters, etc.

• I²C Controller IP Core Brochure
• I²C Controller IP Core Documents