Model No. IPRI2CCMFP001
I²C (Inter-Integrated Circuit) Controller is a two-wire, bi-directional serial bus that provides simple and efficient method of data transmission over a short distance between many devices. Avalon compliant I²C Controller provides an interface between Nios II processor and I²C device. It can work as Master/Slave transmitter or Master/Slave receiver depending on working mode determined by Nios II processor. The I²C Controller IP core incorporates all features required by the latest I²C specification including clock synchronization, arbitration, multi-master systems and Fast-speed transmission mode.
It is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.
- Compatible with Philips I²C(PCF 8584) standard
- Supports both Master and Slave mode
- Automatic detection and adoption to bus interface type
- Multi-master operation
- Byte-by-byte data-transfer is driven by Interrupt or Bit-polling
- Arbitration-lost interrupt with automatic transfer cancellation
- Start/Stop/Repeated Start/Acknowledge generation
- Start/Stop/Repeated Start detection
- Bus-Busy detection
- Supports 7 bit addressing mode
- Operates from wide range of input clock frequencies
- Static synchronous design
- Avalon Bus compliant
|Supported Family||Resource Utilization||Performance ( Avalon Clock - fmax )|
|Cyclone III||300 LE||170MHz|
|Cyclone IV||300 LE||170MHz|
|Cyclone V||300 LE||170MHz|
|Stratix III||210 LE||200MHz|
|Stratix IV||210 LE||200MHz|
|Stratix V||210 LE||200MHz|
|Arria II||155 LE||235MHz|
|Arria V||155 LE||235MHz|
|MAX 10||155 LE||235MHz|
- The SLS I²C Controller IP Core's functionality is verified in ModelSim simulation software using test bench written in verilog HDL.
- The I²C Controller's functionality (as a Master) is tested by interfacing with RTC (Real Time Clock) and I²C EPROM on SLS UP3 Education Kit.
- The I²C Controller's functionality (as a Slave) is tested by communicating with another instance of the same core working as master and also with the SLS I²C Master IP Core on the UP3 Education Kit.
|Contents||Evaluation License||Full Development License|
|License Type||One (1) month evaluation license at no cost
Note: License can be extended for another month after examining request (Evaluation Now)
|Encrypted IP Core Perpetual license for development
Note: Other licensing schemes and source code are also available
|Reference Design||Included for ESDK 1C6 Board||Included for ESDK 1C6 Board|
|Nios II HAL Drivers||Included in Object Code||Included in Object Code
Note: Source Code available separately on request
|Nios II Sample Applications||
|Simulation Library||Altera Modelsim||Altera Modelsim|
|Technical Support||Pre sales support from support team||1 Year integration support for Altera Quartus II|