Avalon compliant I²C Master IP core provides an interface between Nios II processor and an I²C Slave device. It can work as a master transmitter or master receiver depending on working mode determined by Nios II processor. The I²C Master IP core incorporates all features required by the latest I²C specification including clock synchronization, arbitration, multi-master systems and fast-speed transmission mode.
The I²C Master IP core is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.
Compatible with Philips I²C standard
Two transmission speeds are supported; Normal: 100Kbps Fast: 400Kbps
Multi Master Operation
Software programmable clock frequency
Clock stretching and wait state generation
Software programmable acknowledge bit
Interrupt or bit-polling driven byte-by-byte data-transfers
Arbitration lost interrupt, with automatic transfer cancellation
Start/Stop/Repeated Start/Acknowledge generation
Start/Stop/Repeated Start detection
Bus busy detection
Supports 7 and 10bit addressing mode
Operates from a wide range of input clock frequencies
Example LE Usage
I²C Master Core's functionality is verified in modelsim simulation software using test bench written in Verilog HDL
I²C Master IP is also tested by interfacing with RTC (Real Time Clock) and I²C EPROM on SLS UP3 Board
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