The I²C slave IP is fully synthesizable core and compatible with Phillips I²C standard. The IP uses I²C Bus Protocol which helps maximize the hardware efficiency and minimize the interfaces.

The I²C Slave IP Core is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.

Block Diagram:

Features

• Data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode
• Uses two wires to transfer information between devices
• Bi-directional data transfer
• 7-bit addressing format
• Fixed data width of 8 bits
• Data transfer in multiples of bytes
• Interrupt or bit-polling driven byte-by-byte data transfer
• Start/Stop detection
• Operates from a wide range of input clock frequency
• Fully synthesizable

Example LE Usage

Verification

• I²C Slave IP Core's functionality is verified in Modelsim simulation software using test bench in Verilog HDL.

• Evaluation version
  • Encrypted Core
  • One (1) month evaluation license at no cost (from the License Request page )
  • Reference Design with time limited SOF for ESDK 1C6 board (QAR file)
  • Nios II Sample Application
    • Master Read/Write Application
  • Documentation
    • IP Core user guide
    • Hardware and Simulation tutorial
• Full version
  • Encrypted Core
  • One (1) year development license for single project on single node. Other licensing schemes available. Please contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it for details
  • Reference Design with full programming file generation support for ESDK 1C6 board (QAR file)
  • Nios II Sample Application
    • Master Read/Write Application
  • Documentation
    • IP Core user guide
    • Hardware and Simulation tutorial
• View the Eval and full version comparison of the IP core Deliverables.

• I²C Slave is used in many serial communication applications.

• I²C Slave IP Core Brochure
• I²C Slave IP Core Documents