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PS/2 Controller

Model No. IPR0PS2SFP001

Rating: Not Rated Yet
Description

 

 

The PS/2 Controller IP Core provides an interface to standard PS/2 compliant devices such as mouse and keyboard. All a user needs to do is generate a system targeted to hardware and write an assembly or C code to access PS/2. PS/2 Controller purely works on an interrupt basis.

The core has been optimized for popular FPGA devices and its functionality has been verified on the hardware. SLS PS/2 IP Core is an AMPP approved and SOPC builder ready component.

 

Block Diagram:

Features

  • Easy Implementation to communicate with the PS2 device
  • Simple register interface for easy software development
  • Small implementation in terms of FPGA resources
  • Verilog implementation on RTL Level
  • Avalon interface Complaint

 

Example LE Usage

IP Core Supported Families LEs Performance (fmax) Memory Bits
PS/2
Controller
Cyclone
209
118 MHz
0
Cyclone II
204
165 MHz
0
Cyclone III
202
136 MHz
0

 

Verification:

  • PS/2 Controller IP core is tested on UP3 1C6 Education Kit.

Deliverables

  • Evaluation version
    • Encrypted Core
    • One (1) month evaluation license at no cost (from the License Request page )
    • Demonstration
      • PS/2 Keyboard
    • Reference Design with timelimited SOF for ESDK 1C6 Education Kit (QAR file)
    • Nios II Sample Application
      • PS/2 Keyboard
    • Documentation
      • IP Core user guide
      • Design from scratch tutorial
  • Full version
    • Encrypted Core
    • Perpetual license for single project on single node. Other licensing schemes available. Please contact sales@slscorp.com for details
    • Demonstration
      • PS/2 Keyboard
    • Reference Design with full programming file generation for ESDK 1C6 Education Kit (QAR file)
    • Nios II Sample Application
      • PS/2 Keyboard
    • Documentation
      • IP Core user guide
      • Design from scratch tutorial
  • View the Eval and full version comparison of the IP core Deliverables.

Downloads

 

Reviews

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