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PS/2 Controller

Model No. IPR0PS2SFP001

Rating: Not Rated Yet
Description

 

 

The PS/2 Controller IP Core provides an interface to standard PS/2 compliant devices such as mouse and keyboard. All a user needs to do is generate a system targeted to hardware and write an assembly or C code to access PS/2. PS/2 Controller purely works on an interrupt basis.

The core has been optimized for popular FPGA devices and its functionality has been verified on the hardware. SLS PS/2 IP Core is an AMPP approved and SOPC builder ready component.

Block Diagram:

Features:

  • Easy Implementation to communicate with the PS2 device
  • Simple register interface for easy software development
  • Small implementation in terms of FPGA resources
  • Verilog implementation on RTL Level
  • Avalon interface Complaint

Implementation Results:

IP Core Supported Families LEs Performance (fmax) Memory Bits
PS/2
Controller
Cyclone
209
118 MHz
0
Cyclone II
204
165 MHz
0
Cyclone III
202
136 MHz
0

 

Verification:

  • PS/2 Controller IP core is tested on UP3 1C6 Education Kit.

Deliverables:

ContentsEvaluation LicenseFull Development License
License Type One (1) month evaluation license at no cost
Note: License can be extended for another month after examining request (Evaluation Now)
Encrypted IP Core Perpetual license for development
Note: Other licensing schemes and source code are also available
Reference Design ESDK 1C6 Education Kit (QAR file) ESDK 1C6 Education Kit (QAR file)
Demonstration PS/2 Keyboard PS/2 Keyboard
Nios II HAL Drivers Included in Object Code Included in Object Code
Note:Source Code available separately on request
Nios II Sample Applications PS/2 Keyboard PS/2 Keyboard
Technical Documents
  • IP Core User Guide
  • Design from scratch tutorial
  • IP Core User Guide
  • Design from scratch tutorial
Technical Support Pre sales support from support team 1 Year integration support for Altera Quartus II

Downloads:

 

 

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