The Compact Flash Controller IP is designed to access the Physical Compact Flash Card using True IDE and True IDE PIO mode. The True IDE PIO mode can be configured from 3 to 6 using software. The Core supports all compact flash card commands.

The IP Core is provided as an Altera Quartus II Megafunction (SOPC builder ready component) and can be integrated easily into any SOPC builder generated system using the Avalon™ Interconnect Fabric.

Block Diagram:

Features

• Supports True IDE mode for data transfer
• True IDE PIO mode can be configured from 3 to 6
• Avalon Interface Compliant
• Same core can be used to access compact flash of different sizes

Example LE Usage

Verification

• Compact Flash IP core's functionality is verified on Stratix 1S10 kit.

• Evaluation version
  • Encrypted Core
  • One (1) month evaluation license at no cost (from the License Request page )
  • Demonstrations:
    • Compact Flash Card information
  • Reference Design with time limited SOF for Stratix (1S10) (QAR file)
  • Simulation library for Modelsim version 6.3g
  • Nios II Sample Applications
    • Compact Flash Card information
  • Documentation
    • IP Core user guide
    • Design from scratch tutorial
• Full version
  • Encrypted Core
  • One (1) year development license for single project on single node. Other licensing schemes available. Please contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it for details
  • Reference Design with full programming file generation support for Stratix (1S10) (QAR file)
  • Nios II Sample Applications
    • Compact Flash Card information
  • Documentation
    • IP Core user guide
    • Design from scratch tutorial
• View the Eval and full version comparison of the IP core Deliverables.

• Compact Flash IP Core Brochure
• Compact Flash IP Core Documents