Enhanced ClearNAND Controller IP Core is the intermediate stage between NAND Flash memory and master controller. It is designed to have high speed solution to manage NAND Flash application. It supports Open NAND Flash Interface Working Group (ONFI) standard. Two advanced architectures - register based and descriptor based, provides high speed performance, software flexibility, data integrity and device compatibility. Descriptor based architecture reduces amount of CPU intervention.
Enhanced ClearNAND Controller IP Core gives full support for Altera’s SOPC Builder and Qsys based systems and provides communication between processor and NAND Flash device using Avalon interface.
SLS has developed a development Board with Enhanced ClearNAND Flash that can be used to verify the functionality of IP Core.
Supports ONFI EZ NAND 2.3 plus enhanced command set
Supports integrated 32 bit DMA interface for data transfer
Supports interrupt driven functionality
Supports [0-5] asynchronous and [0-5] source synchronous modes of operation
Supports 8 bit data bus
Supports command repeat and auto address increment functionality
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