Enhanced ClearNAND Controller IP Core is the intermediate stage between NAND Flash memory and master controller. It is designed to have high speed solution to manage NAND Flash application. It supports Open NAND Flash Interface Working Group (ONFI) standard. Two advanced architectures - register based and descriptor based, provides high speed performance, software flexibility, data integrity and device compatibility. Descriptor based architecture reduces amount of CPU intervention.

Enhanced ClearNAND Controller IP Core gives full support for Altera’s SOPC Builder and Qsys based systems and provides communication between processor and NAND Flash device using Avalon interface.

Development/Evaluation Board

SLS has developed a development Board with Enhanced ClearNAND Flash that can be used to verify the functionality of IP Core.  

Block Diagram:

Features

• Supports ONFI EZ NAND 2.3 plus enhanced command set
• Supports integrated 32 bit DMA interface for data transfer
• Supports interrupt driven functionality
• Supports [0-5] asynchronous and [0-5] source synchronous modes of operation
• Supports 8 bit data bus
• Supports command repeat and auto address increment functionality
• Configurable buffer depth
• Multi-Plane (interleave) operation support
• Avalon Bus Compliant

Implementation Results on Cyclone IV E

Verification

• The IP Core is tested on SLS USB 3.0 Development Board
• Enhanced ClearNAND Controller IP core's functionality is verified in Altera ModelSim simulation software using test bench written in Verilog HDL

• Evaluation version
  • OpenCore Plus Evaluation
  • One (1) month evaluation license at no cost
  • Time-limited (4 hours) SOF generation support
  • SLS USB 3.0 Development Board Qsys based Reference Design
  • Nios II Command Test Application in 'C'
  • Documentation
    • IP Core user guide
    • Qsys based Hardware and Simulation Tutorial
• Full version
  • Encrypted Core
  • Perpetual license with full version purchase for single project and single site. Other licensing schemes also available.
  • Full programming files generation support
  • SLS USB 3.0 Development Board Qsys based Reference Design
  • Nios II Command Test Application in 'C'
  • Documentation
    • IP Core user guide
    • Qsys based Hardware and Simulation Tutorial

• Enhanced ClearNAND Controller IP Core Documents