ONFI Controller IP Core is the intermediate stage between NAND Flash memory and master controller. It is designed to have high speed solution to manage Raw NAND Flash application. It supports Open NAND Flash Interface Working Group (ONFI) 2.2 standard. Two advanced architectures - register based and descriptor based provides high speed performance, flexibility, data integrity and device compatibility.

The ONFI Controller IP Core gives full support for Altera’s SOPC Builder and Qsys based systems and provides communication between processor and NAND Flash device using Avalon interface.

Snap On Board

SLS has developed ONFI 2.0 HSMC snap on board that can be used with any host board with HSMC interface. Contact This e-mail address is being protected from spambots. You need JavaScript enabled to view it for details.

Block Diagram:

Features

• Supports ONFI 2.3 standard command set
• Supports integrated 32 bit DMA interface selection
• Buffer with configurable buffer depth for read and write operation
• Supports up to 5 NAND Flash device selection*
• Supports 512B, 2KB and 4KB Page Size
• Supports 8 bit data bus
• Supports 4, 8 and 12 bit Error Correction per 512 bytes
• Supports command repeat and auto address increment functionality
• Multiplane (interleave) operation support
• Supports interrupt driven functionality
• Avalon Bus Compliant

Note : *Device selection support can be extended as per requirement on additional charges.

Implementation Results on Cyclone IV E

Implementation Results of ECC on Cyclone IV E

Verification

• The IP Core is tested on
  • SLS USB 3.0 Development Board
  • Altera Cyclone III Development Board (3C120)
  • Altera Cyclone III Starter Kit
  • Altera Stratix IV GX Development Board
• ONFI Controller functionality is verified in Altera ModelSim simulation software using test bench written in Verilog HDL

• Evaluation version
  • OpenCore Plus Evaluation
  • One (1) month evaluation license at no cost
  • Time-limited (4 hours) SOF generation support
  • SLS USB 3.0 Development Board Qsys based Reference Design
  • Nios II Command Test Application in 'C'
  • Documentation
    • IP Core user guide
    • Qsys based Hardware and Simulation Tutorial
• Full version
  • Encrypted Core
  • Perpetual license for single project and single node. Other licensing schemes also available.
  • Full programming files generation support
  • SLS USB 3.0 Development Board Qsys based Reference Design
  • Nios II Command Test Application in 'C'
  • Documentation
    • IP Core user guide
    • Qsys based Hardware and Simulation Tutorial

• ONFI Controller IP Core Documents