ONFI Controller IP Core is the intermediate stage between NAND Flash memory and master controller. It is designed to have high speed solution to manage Raw NAND Flash application. It supports Open NAND Flash Interface Working Group (ONFI) 2.2 standard. Two advanced architectures - register based and descriptor based provides high speed performance, flexibility, data integrity and device compatibility.
The ONFI Controller IP Core gives full support for Altera’s SOPC Builder and Qsys based systems and provides communication between processor and NAND Flash device using Avalon interface.
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