| 1. | What is the difference between the evaluation OpenCore USB 2.0 Device IP Core and the full license SLS USB 2.0 Device IP Core? |
|
The SLS USB 2.0 solution contains several additional deliverables that are not provided in the OpenCore USB 2.0 IP package: | |
| 2. | What can I do with the evaluation version of your core? How does this compare to the full production version? |
| The evaluation version of the USB 2.0 IP Core is the OpenCore plus evaluation of this megafunction and it operates in tethered mode. This means that the JTAG cable has to be connected between the board and the host computer (that runs the Quartus II programmer) for the duration till the hardware evaluation period expires. Also, the OpenCore plus hardware evaluation feature adds additional logic to the design that may affect the timing and fitting of the design. | |
| 3. | What are the minimum system requirements to integrate the evaluation or full license SLS USB 2.0 IP Core? |
|
The minimum system requirements for integrating evaluation or full license SLS USB 2.0 IP Core are listed below : | |
| 4. | Do you provide the source code for your IP |
| The standard version of the SLS USB 2.0 IP Core does not come with the source code but can be provided on request and payment of a separate license fee. However, some software applications ship with full source and are listed in the deliverables. | |
| 5. | How many endpoints does the SLS USB 2.0 IP Core support? |
| The standard IP version is preconfigured for three (3) endpoints (Control, Bulk In and Bulk Out). Up to a total of fifteen (15) endpoints are supported and may be added as per design requirements at additional cost. | |
| 6. | Can I get the open source code for HAL? |
| Yes, open source for the HAL can be licensed at extra cost. | |
| 7. | Can I customize the vendor ID in the full version? |
| Yes, we provide the utility to customize product ID and vendor ID in the full version SLS USB 2.0 IP core. | |
| 8. | How do I verify core functionality in hardware as well as in simulation? |
| The SLS USB 2.0 IP Core package includes an embedded evaluation demonstration board that can be used to verify the core functionality in hardware. The package also includes a Modelsim precompiled library to simulate the design and verify basic transactions. | |
| 9. | We plan to use uC/USB (A Micrium product) with the SLS USB 2.0 IP core. Can you please confirm compatibility? |
| The SLS USB 2.0 IP Core, as with Nios II, is compatible with the Micrium uC RTOS. One can modify the source or drivers to support different operating systems as a design service. Please contact us at info@slscorp.com to request a quote. Note that we require customers to provide us with access to their OS of choice so that we may do the porting and driver development. | |
| 10. | What is the minimum clock requirement to operate at 480 Mbps? |
| 60 MHz should be the clock to the core clock for successful operation at 480 Mbps. |
| 1. | How do I obtain the license for evaluation package/full production package? |
| Evaluation licenses for SLS IP Cores can be requested by visiting http://www.slscorp.com/pages/ipLicenseinfo.php and following the instructions provided. The full production package license is provided via email after purchasing the core. | |
| 2. | How do I set up the SLS USB 2.0 IP Core license? |
| Please refer to the set-up instructions in the readme.txt file provided in the core package. Instructions are also provided in the email received with the license file from license@slscorp.com. | |
| 3. | I tried to compile the USB 2.0 reference design provided in the SLS USB 2.0 IP Core package. I have the license file, but I still cannot open the USB 2.0 reference design in the Quartus II software. |
| Please check your version of Quartus II software. The reference designs provided in the IP package support Quartus II version 6.0 or higher. You can upgrade your software version by visiting http://www.altera.com/download. Also, although Altera may update Quartus, the reference design may not be immediately updated. | |
| 4. | I created a project using the SLS USB 2.0 IP Core, but on compilation or analysis and synthesis, I see the following error "Error: Can't open encrypted VHDL or Verilog HDL file." |
This error can arise if the license file is missing or incorrect. Please go to Tools menu and select “License set up” and give the path for the USB 2.0 IP license file in the “License file” box. See the figure below: If you have provided the path for Quartus license then insert a semicolon (;) between the two license file paths. See the figure below: 
| |
| 5. | I am having trouble installing the SLS USB 2.0 IP Core update I just received. |
| Please uninstall all the SLS USB 2.0 IP Core package components on the machine, manually clean the folders and then re-install the update. This will be a clean installation and will not create any problems. |
| 1. | How do I verify core functionality in hardware as well as in simulation? |
| The SLS USB 2.0 IP Core package includes an embedded demonstration board that can be used to verify the core functionality in hardware. The package also includes a Modelsim precompiled library to simulate the design and verify basic transactions. | |
| 2. | I start the test application as per the instructions in the manual, but I still get a “USB device not recognized.” Message. How can I solve this problem? Is there some problem with the files I downloaded? |
|
There is nothing wrong with the application or the files downloaded. Please follow the procedure below in exact sequence:
In most cases, it is a faulty cable or some disconnect on the D+/D- lines. | |
| 3. | Where does 60 MHz clock come from? |
| In the reference design provided, the 60 MHz clock comes from the PHY chip. It is recommended to use the same clock for the PHY chip and the IP core to avoid synchronization issues. | |
| 4. | Can we use development board clock for the core? |
| Yes, the development board clock can definitely be used with the core if the clock synchronization between PHY and core clock is taken care of in the design. | |
| 5. | What size transmit and receive buffers are needed for the bulk in/out endpoint? |
| The buffer size depends upon the data memory provided in the Nios project and what the application demands. | |
| 6. | Can the Transmit and Receive operations run in background or are they the primary thread? |
| No, Transmit and Receive operations cannot run in background. Both Read and Write operations of the HAL driver are in the blocking mode on the NIOS side. | |
| 7. | When performing Bulk operation, how do I determine how many bytes were received? |
| The HAL driver API on the Nios side returns the count value of the number of bytes received. | |
| 8. | Is there a method to know if the device is successfully enumerated? If not, can I force enumeration? |
| Yes, the speed negotiation register may be read and the appropriate bit extracted. Yes enumeration may be forced using the disconnect API. This will force the PHY chip to disconnect, and reconnection will occur using the connect API. | |
| 9. | Does the USB 2.0 IP core support packet size adjustment according to USB speed? |
| Yes, the USB 2.0 core will adjust speed based on which mode is selected. When enumerated the core supports 64Byte packets in Full speed mode and 512Bytes in Hi-speed mode. |