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| INTRODUCTION | |
FEATURES | |
APPLICATION |
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| Introduction |
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The 8051 Master IP Core from SLS implements industry standard
8051 Microcontroller for Altera devices.
The core is fully synthesizable and is 10 times faster than
industry standard 8051.
The IDE provided along with the 8051 IP is based on SDCC compiler, CAS assembler and eclipse IDE.
Its user friendly interface makes development on 8051 appealing, eventually leading to faster and better codes.
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| Features |
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- 8051 IP
- Instruction set is compatible to the industry standard 8051 Micro Controller
- Up to 10 times faster than industry standard 8051
- Supports four ports, two separate demultiplexed ports (input, output) and two bidirectional ports
- Up to 64 Kbytes of External ROM, 4 Kbytes of Internal ROM, 64 Kbytes of External RAM, and 128 bytes of Internal RAM
- Operates at system clock frequency up to 36 MHz
- Fully synthesizable design
- 8051 IDE
- Designing & Compiling 8051 Project
- Integrates Text editor, SDCC Cross Compiler, CASS Assembler and Emulator for C and Assembly programs
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| Example LE Usage |
| Supported Families |
LEs |
Memory Bits |
| Cyclone |
4996 |
33840 |
| Cyclone II |
4937 |
33840 |
| Cyclone III |
4935 |
33840 |
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| Verification: |
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8051 Master IP's functionality is tested on ESDK 1C6 board
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| Deliverables |
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| IDE Block Diagram: |
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Related Products
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Downloads
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