8051 Master IP Core

INTRODUCTION |

FEATURES |

APPLICATION

Introduction

The 8051 Master IP Core from SLS implements industry standard 8051 Microcontroller for Altera devices. The core is fully synthesizable and is 10 times faster than industry standard 8051.

The IDE provided along with the 8051 IP is based on SDCC compiler, CAS assembler and eclipse IDE. Its user friendly interface makes development on 8051 appealing, eventually leading to faster and better codes.

IP Features

Avalon Interconnection Compliant
Instruction set is compatible to industry standard 8051 micro controller
Operates at system clock frequency upto 36 MHz
Fully synthesizable
Up to 10 times faster due to completely new architecture
Four ports available, two separate demultiplexed ports (input, output) other two are bidirectional
Upto 64 Kbytes of ROM, 128 bytes of Internal RAM and 64 Kbytes of External RAM

IDE Features

Creation of Project
Text editor of C and Assembly programs
SDCC Cross Compiler
CASS Assembler
Emulator
Dialogue box for advanced Compilation

IDE :

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