Graphics LCD Controller supports LCD display with user programmable resolutions and video timings, thus providing capability with almost all available LCD displays. The core supports number of color modes including 32bpp, 24bpp, 16bpp, and 8bpp (Grayscale). The core can interrupt the host on each horizontal and/or vertical sync pulse.

The core has been optimized for popular FPGA devices and its functionality has been verified on the hardware. It is provided as Altera Quartus II Mega function (Altera SOPC Builder ready component) and can be integrated easily into any SOPC Builder generated system using Nios^® II Avalon bus.