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| Introduction |
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The SD Host Controller (SDHC) IP Core implements SD memory card host controller compatible with SD Physical Layer v2.0. SDHC
IP core support standard SD Memory Card as well as SD High Capacity Card (SDHC). Fully register based configuration makes it very
easy to integrate in wide range of application. The SLS SD Host controller IP gives full support for Altera's SOPC based system and
provides communication between Altera's Avalon Bridge and Secure Digital (SD) Card.
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| Features |
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- Follows SD Physical Layer Specification v2.0
- Supports SD High Capacity Card ( SDHC )
- Supports both SD 1-bit and 4-bit mode for data communication
- Internal variable length FIFO for data buffering
- Variable SD Clock frequency selection using software
- Hardware implementation of CRC7 and CRC16 module for generation and verification
- Variable block length support
- Multiple block transfer support
- Support for interrupt driven functionality
- Integrated 32bit DMA interface for data transfer
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| Example LE Usage |
| IP Core |
Supported Families |
LEs |
Performance (fmax) |
Memory Bits |
| SDHC |
Cyclone |
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| Cyclone II |
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| Cyclone III |
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| Stratix II |
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| Please Note: The implementations results can change upon core revision. Please contact support@slscorp.com for latest figures |
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| Verification |
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- SD Host Controller IP core's functionality is verified on CoreCommander (Cyclone III) board.
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| Deliverables |
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Related Products
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Downloads
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