The SD Host Controller (SDHC) IP Core implements SD memory card host controller compatible with SD Physical Layer v2.0. SDHC
IP core support standard SD Memory Card as well as SD High Capacity Card (SDHC). Fully register based configuration makes it very
easy to integrate in wide range of application. The SLS SD Host controller IP gives full support for Altera's SOPC based system and
provides communication between Altera's Avalon Bridge and Secure Digital (SD) Card.
Features
Follows SD Physical Layer Specification v2.0
Supports SD High Capacity Card ( SDHC )
Supports both SD 1-bit and 4-bit mode for data communication
Internal variable length FIFO for data buffering
Variable SD Clock frequency selection using software
Hardware implementation of CRC7 and CRC16 module for generation and verification
Variable block length support
Multiple block transfer support
Support for interrupt driven functionality
Integrated 32bit DMA interface for data transfer
Example LE Usage
IP Core
Supported Families
LEs
Performance (fmax)
Memory Bits
SDHC
Cyclone
~ 2000
120 MHz
8192
Cyclone II
~ 2000
135 MHz
8192
Cyclone III
~ 2000
135 MHz
8192
Stratix II
~ 2000
137 MHz
8192
Please Note: The implementations results can change upon core revision. Please contact support@slscorp.com for latest figures
Verification
SD Host Controller IP core's functionality is verified on CoreCommander (Cyclone III) board.
US
