AC’97 IP Core

INTRODUCTION |

FEATURES |

APPLICATION

Introduction

Avalon compliant AC’97 Controller IP Core provides an interface between a Nios II processor and AC’97. It supports one AC’97 codec, with 6 output and 3 input channels. The core is fully AC’97 Rev.2.1 compliant.

The core is provided as an Altera Quartus II Megafuction (SOPC builder ready component) and can be integrated easily into any SOPC builder generated system using the Avalon^TM Interconnect Fabric.

SLS also provides you with Santa Cruz Audio Codec (AC’97) snap on board.

Features

Avalon Bus Compliant
Compliant with AC’97 Revision 2.1(LM4550)
Variable and Fixed Sample Rate Support, up 48 KHz
16, 18 and 20 bit Sample Size Support
6 Output Channel Surround Sound Support
Stereo Input channel Support
Mono Microphone Channel Support
Implementation in Verilog RTL
Fully Synthesizable

Target Application

Embedded Applications
Home entertainment consumer electronics

Verification

The SLS AC’97 Controller IP Core's functionality is verified in ModelSim simulation software using test bench written in Verilog HDL

Deliverables

Encrypted RTL in verilog
Test Bench in Verilog AC’97
Reference Design/s for standard boards
Sample Application (.c file) for the Nios II Processor
Technical Documents

Related Products

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USB 2.0 Embedded Development Board (Cyclone III FPGA)

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