Menu
Home
 US
Home | Shopping Cart | Login | Contact Us |
 
SLS - About SLS - Contact Us
ABOUT US   |   PRODUCTS   |   IP CORES   |   SERVICES   |   DOWNLOADS   |   LICENSING
Logic Analyzer
 Communication
     USB 3.0 Device 
     USB 2.0 Device 
     USB 2.0 Host 
     USB 1.1 
     Ethernet MAC 10/100 
 Interface
     I2C Controller 
     I2C Master 
     I2C Slave 
     I2S Controller 
     AC’97 Controller 
 Display
     VGA/LCD Controller 
     Graphics LCD Controller 
     Touch Panel Controller 
 Memory
     SD Host Controller 
     Compact Flash Controller 
 Processor
     8051 Master 
 Legacy
     PS/2 Controller 
You are here: Home> IP Cores > Communication Cores >Ethernet MAC 10/100
Ethernet MAC 10/100
          
View Full size
INTRODUCTION | FEATURES
Introduction

The Ethernet MAC 10/100 IP is designed for implementation of CSMA/CD in accordance with the IEEE 802.3 and 802.3u standards. The core is a 10/100 Media Access Controller (MAC) for Altera devices that supports half and full duplex modes. The core connects to any industry standard ethernet PHY device via MII (Media Independent Interface for 10/100 Mbps applications) and to a user application via the Avalon bus interface.

The core has been optimized for popular FPGA devices and its functionality has been verified on the real hardware. It is provided as Altera Quartus II Mega Function (Altera SOPC Builder ready component) and integrates easily into any SOPC Builder generated system using Nios® II Avalon bus.

Do not have Ethernet interface on your Development Board ?  Click here for a System Level Solution!

Features
  •  Performs MAC layer function as per IEEE 802.3 and Ethernet standard
  •  Supports full duplex and half duplex modes
  •  Supports 10/100 Mbps speed
  •  Flow control and generation of control frames in full duplex mode (IEEE 802.3x)
  •  IEEE 802.3 Media Independent Interface(MII)
  •  Collision detection and auto re-transmitting on collision in half duplex mode (CSMA/CD protocol)
  •  Complete status for TX/RX packets
  •  32 bit CRC generation and checking
  •  Delayed CRC generation
  •  Preamble generation and removal
  •  Automatically pad short frames on transmit
  •  Detection of too long or too short packets length limits
  •  Possible transmission of packets those are bigger than standard packets
  •  Automatic packet abortion on excessive deferral limit, too small inter packet gap, when enabled internal RAM  for holding 128 TX/RX buffer descriptors
  •  Transmit, receive FIFO of 32 x 16(width x depth)
  •  Interrupt generation
Example LE Usage
IP Core Family LE Memory bits Performance
Ethernet Cyclone II 2347 9216 169 MHz
Cyclone III 2351 9216 134 MHz
Verification
  • Ethernet IP Core functionality is tested on CoreCommander (Cyclone III) board by interfacing with Ethernet PHY chip on the Ethernet Add On board.
Deliverables
  • Evaluation version  
    • Encrypted Core
    • One (1) month evaluation license at no cost (from the License Request page )
    • Reference Design with time limited SOF for CoreCommander with Ethernet Add On board (QAR file)
    • Nios II Sample Application
      • UDP ECHO
    • Documentation
      • IP Core user guide
      • Design from scratch tutorial
      • Ethernet Add On Board Reference Manual
    • Utilities
      • UDP ECHO
  • Full version
    • Encrypted Core
    • One (1) year development license for single project on single node. Other licensing schemes available. Please contact sales@slscorp.com for details
    • Reference Design with full programming file generation support for CoreCommander with Ethernet Add On board (QAR file)
    • Simulation library for Modelsim version 6.3g
    • Nios II Sample Application
      • UDP ECHO
    • Documentation
      • IP Core user guide
      • Design from scratch tutorial
      • Ethernet Add On Board Reference Manual
    • Utilities
      • UDP ECHO
  • View the Eval and Full version comparison of the IP core Deliverables.
  • Related Products

     
    Ethernet Snap On Board
    CoreCommander board (Cyclone III)
    Logic Analyzer and Pattern Generator
    Downloads

    Footer
    Privacy Policy | Site Map Copyright© 2010 System Level Solutions All Rights Reserved.