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You are here: Home> IP Cores > Interface Cores >Ethernet 10/100
Ethernet 10/100
          
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INTRODUCTION | FEATURES
Introduction

The IPETH100M - Ethernet MAC 10/100 is designed for implementation of CSMA/CD in accordance with the IEEE 802.3 and 802.3u standards. The core is a 10/100 Media Access Controller (MAC) for Altera devices that supports half and full duplex modes. The core connects to any industry standard ethernet PHY device via MII (Media Independent Interface for 10/100 Mbps applications) and to a user application via the Avalon bus interface.

The core has been optimized for popular FPGA devices and its functionality has been verified on the real hardware. It is provided as Altera Quartus II Megafunction (Altera SOPC Builder ready component) and integrates easily into any SOPC Builder generated system using Nios® II Avalon bus.

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Features
  •  Performs MAC layer function as per IEEE 802.3 and Ethernet standard
  •  Flow control and generation of control frames in full duplex mode (IEEE 802.3x)
  •  IEEE 802.3 media Independent interface (MII)
  •  Collision detection and auto re-transmitting on collision in half duplex mode (CSMA/CD protocol)
  •  Complete status for TX/RX packets
  •  32 bit CRC generation and checking
  •  Delayed CRC generation
  •  Preamble generation and removal
  •  Automatically pad short frames on transmit
  •  Detection of too long or too short packets length limits
  •  Length limits
  •  Pause timer & slot timer
  •  Possible transmission of packets those are bigger than standard packets
  •  Full duplex support
  •  Compatible to 10/100 Mbps speed
  •  Automatic packet abortion on excessive deferral limit, too small inter packet gap, when enabled internal RAM  for holding 128 TX/RX buffer descriptors
  •  Transmit, receive FIFO of 32 x 16(width x depth)
  •  Interrupt generation
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