The Ethernet MAC 10/100 IP is designed for implementation
of CSMA/CD in accordance with
the IEEE 802.3 and 802.3u standards. The core is
a 10/100 Media Access Controller (MAC) for Altera
devices that supports half and full duplex modes.
The core connects to any industry standard ethernet
PHY device via MII (Media Independent Interface
for 10/100 Mbps applications) and to a user application
via the Avalon bus interface.
The
core has been optimized for popular FPGA devices
and its functionality has been verified on the real
hardware. It is provided as Altera Quartus II Mega Function
(Altera SOPC Builder ready component) and integrates
easily into any SOPC Builder generated system using
Nios® II Avalon bus.
Do not have Ethernet interface on your Development
Board ? Click here for a System Level Solution!
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