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You are here: Home> IP Cores > Interface Cores >I²C Master
I²C Master
          
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INTRODUCTION | FEATURES | APPLICATION
Introduction

The I²C master IP from SLS provides interface between Avalon master and an I²C Slave device. The Core is compatible with Phillips I²C standard. The IP core incorporates all features required by the latest Phillips I²C specification, version 1.0, including clock synchronization, arbitration, multi-master systems and Fastspeed transmission mode.

Features
  • Compatible with Philips I²C standard
  • Multi-Master Operation
  • Software programmable clock frequency
  • Software programmable acknowledgement bit
  • Bit polling driven byte-by-byte data-transfers
  • Arbitration-lost detection, with automatic transfer cancellation
  • Start/Stop/Repeated Star/Acknowledgement generation
  • Start/Stop/Repeated Start detection
  • Bus busy detection
  • Operates from a wide range of input clock frequencies
  • Static synchronous design
  • Fully synthesizable
Applications
  • Interface with microcontroller
  • Communication System
Verifications
  • I²C Master Core's functionality is verified in modelsim simulation software using test bench written in Verilog HDL
  • I²C Master IP is also tested by interfacing with RTC (Real Time Clock) and I²C EPROM on SLS UP3 Board
 Appication Example :  Create a system that incorporates 32 bit NIOS Processor, I²C Master IP, SRAM and some display module View Full size
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