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| INTRODUCTION | |
FEATURES | |
APPLICATION |
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| Introduction
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The I²C slave IP is fully synthesizable core and compatible with Phillips I²C standard.
The IP uses I²C Bus Protocol which helps maximize the hardware efficiency
and minimize the interfaces.
The I²C Slave IP Core is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.
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| Features |
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- Data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode
- Uses two wires to transfer information between devices
- Bi-directional data transfer
- 7-bit addressing format
- Fixed data width of 8 bits
- Data transfer in multiples of bytes
- Interrupt or bit-polling driven byte-by-byte data transfer
- Start/Stop detection
- Operates from a wide range of input clock frequency
- Fully synthesizable
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| Example LE Usage |
| IP Core |
Supported Families |
LEs |
Performance (fmax) |
Memory Bits |
| I²C Slave |
Cyclone |
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| Cyclone II |
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| Cyclone III |
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| Verification |
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- I²C Slave IP Core's functionality is verified in Modelsim simulation software using test bench in Verilog HDL.
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| Deliverables |
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| Application |
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- I²C Slave is used in many serial communication applications.
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Related Products
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