I²C Slave IP Core

INTRODUCTION |

FEATURES |

APPLICATION

Introduction

The I²C slave IP form SLS is fully synthesizable core compatible with Phillips I²C Standard. This IP core uses I²C Bus Protocol which helps maximize the hardware efficiency and minimize the interfaces. Avalon Master reads data from the I²C Slave via Avalon Bus and displays on the console. Slave receives data from I²C Master through SCL and SDA lines.

Features

Compatible with Philips I²C standard
Two transmission speeds are supported 100Kbps:Normal and 400Kbps:Fast
Interrupt or bit-polling driven byte-by-byte data-transfers
Start/Stop/Repeated Start/Acknowledgement generation
Start/Stop/Repeated Start detection
Supports 7 addressing mode
Operates from a wide range of input clock frequencies
Static synchronous design
Fully synthesizable

Application

I²C Slave is used in many serial communication applications

Verification

I²C Slave Core's functionality is verified in modelsim simulation software using test bench in Verilog HDL

Appication Example : Create a system that incorporates 32 bit NIOS Processor, I²C Master IP, SRAM and I²C Slave IP.

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