I²S IP Core

INTRODUCTION |

FEATURES |

APPLICATION

Introduction

I²S Controller is designed to transfer audio data to and from Audio codec. It can be configured as both Master and Slave mode using software. The I²S IP is Phillips Inter IC Sound (I²S) specification compliant core for Altera devices.

It is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.

Features

8-bit and 16-bit sampling data width support
Variable sampling rate support
Used in both master/slave mode
Internal two 64 x 32 bit FIFO for data buffering
32-bit DMA engine for both data transmit and receive for reducing CPU overhead
Transmit and Receive Operation
Compliant with the Avalon bus
Left and Right channel support

Example LE Usage

IP Core

Supported Families

LEs

Performance (f_max)

Memory Bits

I²S
Controller

Cyclone

812

170 MHz

4096

Cyclone II

786

186 MHz

4096

Cyclone III

793

188 MHz

4096

Verification

I²S IP Core functionality is tested on NEEK kit.

Deliverables

Evaluation version

Encrypted Core
One (1) month evaluation license at no cost (from the License Request page )
Reference Design with time limited SOF for NEEK kit(QAR file)
Nios II Sample Application

I²S application

Documentation

IP Core user guide
Design from scratch tutorial

Full version

Encrypted Core
One (1) year development license for single project on single node. Other licensing schemes available. Please contact sales@slscorp.com for details
Reference Design with full programming file generation support for NEEK kit (QAR file)
Nios II Sample Application

I²s application

Documentation

IP Core user guide
Design from scratch tutorial

View the Eval and full version comparison of the IP core Deliverables.

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Embedded System Development Kit (Cyclone FPGA)

Downloads