I²S IP Core

INTRODUCTION |

FEATURES |

APPLICATION

Introduction

The I²S IP is Phillips Inter IC Sound (I²S) specification compliant core for Altera devices. The core supports variable data width and sampling frequency between 4 KHz to 96 KHz.

Features

Philips Inter IC Sound (I²S) specification compliant
Provides selection for Master/slave mode
Transmit and Receive operations both in Master or Slave Mode
Avalon Interface Compliant
Support 8/16/24/32 digital audio data width
High quality Sampling rate between 4 KHz to 96 KHz in 1 KHz increments
4, 8,16,32,64,128,256,512 FIFO depth support
Supports Left and Right Channel selection

Application

It is used in communication with any I²S compliant audio codec to transmit or receive digital audio data

Verification

I²S Core's functionality is verified in modelsim simulation software using test bench in Verilog HDL

Related Products

Embedded Systems Development Kit (Cyclone FPGA)

USB 2.0 Embedded Development Board (Cyclone III FPGA)

Logic Analyzers and Pattern Generators

Downloads