The USB1.1 IP core is a universal serial bus (USB)
function controller that provides a USB full-speed
function interface that meets the USB1.1 Specification.
This IP core is available with 3 standard
endpoint ( 1 CTRL, 1 BULK IN, 1 Bulk OUT ) configuration
with maximum payload size. Each endpoint requires
a FIFO to be associated with it. The FIFO size for
Endpoint 0 is fixed at 64 bytes and For Bulk IN
and
OUT FIFO is fixed at 128bytes.The core has been
optimized for popular FPGA devices and
its functionality has been verified in the real
hardware.
The IP core is user-configurable for up to 15 IN
endpoints and up to 15 OUT endpoints, in addition
to Endpoint 0.These additional endpoints can be
individually programmed for Bulk/Interrupt or Isochronous
transfers.
It contains an USB serial interface engine, FIFO
group, control/status register group, and Avalon
bus interface, making it easy to design an USB system.
US
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