USB 2.0 FAQ

Pre-sales


1.	What is the difference between the evaluation OpenCores USB 2.0 Device IP Core and the full license SLS USB 2.0 Device IP Core?
2.	Do you have a USB 2.0 Host Core?
3.	What can I do with the evaluation version of your core? How does this compare to the full production version?
4.	I want a hardware only solution for my product. I do not intend to use Nios II processor or SOPC builder. Do you have a solution?
5.	Do you provide the source code for your IP?
6.	How many endpoints does the SLS USB 2.0 IP Core support?
7.	Can I get the open source code for HAL?
8.	Can I customize the vendor ID in the full version?
9.	How do I verify core functionality in hardware as well as in simulation?
10.	We plan to use uC/USB (A Micrium product) with the SLS USB 2.0 IP core. Can you please confirm compatibility?
11.	I am using USB 2.0 Device with Avalon interface (USB20HR) now. Do I need to pay extra charges If I want to switch to use USB 2.0 Device with FIFO interface (USB20HF)?

IP Implementation

1.	How do I verify core functionality in hardware as well as in simulation?
2.	I start the test application as per the instructions in the manual, but I still get a "USB device not recognized." Message. How can I solve this problem? Is there some problem with the files I downloaded?
3.	Where does 60 MHz clock come from in USB20HR reference design?
4.	Can I use 70 MHz system clock while designing a USB20HR system in SOPC builder?
5.	How do I generate 19.2 MHz clock and why it is needed in USB20HR system provided in the package?
6.	Can we use development board clock for the USB20HR core?
7.	What size transmit and receive buffers are needed for the bulk in/out endpoint of USB20HR Core?
8.	Can the Transmit and Receive operations run in background or are they the primary thread for USB20HR Core?
9.	When performing Bulk operation, how do I determine how many bytes were received?
10.	Is there a method to know if the device is successfully enumerated? If not, can I force enumeration?
11.	Does the USB20HR IP core support packet size adjustment according to USB speed?
12.	Do I need the Clock Crossing Bridge while designing a USB20HR System in SOPC builder?
13.	Does the Data Catche create a problem?
14.	Can you provide NIOS2 USB HOST Stack? Is it necessary to run one OS for the USB?
15.	The USB20HR IP Core that I have does not support UTMI interface. How do I enable that?

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Licensing/Installation

Answers

Pre-sales

1.	What is the difference between the evaluation OpenCores USB 2.0 Device IP Core and the full license SLS USB 2.0 Device IP Core?
	The SLS USB 2.0 Device IP Core contains several additional features listed below that are not provided in the OpenCores USB 2.0 IP package: SLS USB 2.0 Device IP Core is delivered with HAL API that gives Nios II support The IP package includes Windows drivers Support contract: SLS IP Core is fully supported by a team of design engineers The SLS USB 2.0 Device IP Core contains hooks for passing USB compliance testing

2.	Do you have a USB 2.0 Host Core?
	Yes, we do have an Embedded USB 2.0 Host Controller IP core that supports memory sticks. The evaluation version of the core can be downloaded from http://www.slscorp.com/pages/usb20hostcontroller.php.

3.	What can I do with the evaluation version of your core? How does this compare to the full production version?
	The evaluation version of the USB 2.0 IP Core is the OpenCore plus evaluation of this megafunction and it operates in tethered mode. This means that the downloaded program will remain inside the hardware for a particular amount of time only. Once the program is downloaded and timeout occurs, the hardware evaluation IP Core will stop working. Also, the OpenCore plus hardware evaluation feature adds additional logic to the design that may affect the timing and fitting of the design. Therefore, you can check whether the core meets your design requirements with the evaluation version with this time limited feature and then confidently go for full production version for your final product. Initially, one (1) month evaluation license is provided which can be extended upon request and justification of the product evaluation needs.

4.	I want a hardware only solution for my product. I do not intend to use Nios II processor or SOPC builder. Do you have a solution?
	Yes, we do have a solution. A variant of USB 2.0 Device Controller core - USB20HF has a FIFO interface. This means, it communicates with external world using FIFOs instead of Avalon interface. This version occupies minimum of FPGA resources and it can be used for simpler and hardware based USB 2.0 solutions. The evaluation version of the core can be downloaded from: http://www.slscorp.com/pages/ipusb20hfsls.php

5.	Do you provide the source code for your IP?
	The standard version of the SLS USB 2.0 IP Core does not come with the source code but can be provided on request and payment of a separate license fee. However, some software applications ship with full source and are listed in the deliverables.

6.	How many endpoints does the SLS USB 2.0 IP Core support?
	The standard IP version is preconfigured for three (3) endpoints (Control, Bulk In and Bulk Out). Up to a total of fifteen (15) endpoints are supported and may be added as per design requirements at additional cost.

7.	Can I get the open source code for HAL?
	Yes, open source for the HAL is included in the full version of the core.

8.	Can I customize the vendor ID in the full version?
	Yes, we provide the utility to customize product ID and vendor ID in the full version SLS USB 2.0 IP core.

9.	How do I verify core functionality in hardware as well as in simulation?
	The SLS USB 2.0 IP Core package includes an embedded evaluation demonstration board that can be used to verify the core functionality in hardware. The package also includes a Modelsim precompiled library to simulate the design and verify basic transactions.

10.	We plan to use uC/USB (A Micrium product) with the SLS USB 2.0 IP core. Can you please confirm compatibility?
	The SLS USB 2.0 IP Core, as with Nios II, is compatible with the Micrium uC RTOS. One can modify the source or drivers to support different operating systems as a design service. Please contact at info@slscorp.com to request a quote. Note that we require customers to provide us with access to their OS of choice so that we may do the porting and driver development.

11.	I am using USB 2.0 Device with Avalon interface (USB20HR) now. Do I need to pay extra charges If I want to switch to use USB 2.0 Device with FIFO interface (USB20HF)?
	No, there will be no extra charges if you wish to switch over from USB20HR version to USB20HF version of the core.

IP Implementation

1.	How do I verify core functionality in hardware as well as in simulation?
	The SLS USB 2.0 IP Core package includes the CoreCommander board that can be used to verify the core functionality in hardware. The package also includes a Modelsim precompiled library to simulate the design and verify basic transactions.

2.	I start the test application as per the instructions in the manual, but I still get a "USB device not recognized." Message. How can I solve this problem? Is there some problem with the files I downloaded?
	There is nothing wrong with the application or the files downloaded. After successfully downloading the .elf file, run the usbview utility to verify the USB device connection. If the device is not connected properly, you will see the message "Enumeration failed" and in such case you will find the the message USB device not recognized. To solve this error, follow the steps below: Plug in one end of the 'b' type USB cable to the device and other end to the PC. Check that the USB cable comply with the specification and it is not faulty. Connect the USB cable to another USB port.
3.	Where does 60 MHz clock come from in USB20HR reference design?
	In the reference design provided, the 60 MHz clock comes from the PHY chip. It is recommended to use the same clock for the PHY chip and the IP core to avoid synchronization issues.

4.	Can I use 70 MHz system clock while designing a USB20HR system in SOPC builder.
	Yes, you can use 70 MHz clock.

5.	How do I generate a 19.2 MHz clock and why it is needed in USB20HR system provided in the package?
	You can generate a 19.2 MHz clock from PLL and it is exported. If you do not want to use crystal on the CoreCommander board for driving the PHY chip in clock signal, this clock signal is used.

6.	Can we use development board clock for the USB20HR Core?
	Yes, the development board clock can definitely be used with the core if the clock synchronization between PHY and core, clock is taken care of in the design.

7.	What size of Transmit and Receive buffers are needed for the Bulk IN/OUT endpoint of USB20HR Core?
	The buffer size depends upon the data memory provided in the Nios II project and what the application demands.

8.	Can the Transmit and Receive operations run in background or are they the primary thread for USB20HR Core?
	No, Transmit and Receive operations cannot run in background. Both Read and Write operations of the HAL driver are in the blocking mode on the NIOS side.

9.	When performing Bulk operation, how do I determine how many bytes were received?
	The HAL driver API on the Nios side returns the count value of the number of bytes received.

10.	Is there a method to know if the device is successfully enumerated? If not, can I force enumeration?
	Yes, the speed negotiation register may be read and the appropriate bit extracted. Yes enumeration may be forced using the disconnect API. This will force the PHY chip to disconnect, and reconnection will occur using the connect API.

11.	Does the USB20HR IP core support packet size adjustment according to USB speed?
	Yes, the USB 2.0 core will adjust speed based on which mode is selected. When enumerated, the core supports 64Byte packets in Full Speed mode and 512Bytes in Hi Speed mode.

12.	Do I need the Clock Crossing Bridge while designing a USB20HR System in SOPC builder?
	No, you do not need to use the Clock Crossing Bridge compulsorily with the USB20HR system in SOPC builder. This is optional and system can be generated without it.

13.	Does the Data Catche create a problem?
	Data cache can not create any hardware related problem. It can give mismatch of data value if cache is not handled properly on Nios II application side.

14.	Can you provide Nios II USB HOST Stack? Is it necessary to run one OS for the USB?
	We do provide USB Host Stack, but not in source code form. Also, no OS is required since our stack is a standalone stack.

15.	The USB20HR IP Core that I have does not support UTMI interface. How do I enable that?
	The USB20HR IP Core does not come with direct support of UTMI interface. However, it is possible to have the UTMI interface enabled by replacing a existing TCL file. Please download and extract the TCL file for UTMI interface from: http://www.slscorp.com/download/sls_avalon_usb20hr_hw.zip. Delete the existing TCL file located at ../hardware/component folder and copy the extracted file at this location. Restart the Quartus II software and SOPC Builder. After updating the project you will be able to see the UTMI interface enabled in the USB20HR IP Core.