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| INTRODUCTION | |
FEATURES | |
DELIVERABLES |
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| Introduction |
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The SLS USB 3.0 Device core is the SuperSpeed core that supports connectivity between TI USB3.0 Phy (TUSB1310 ) and Altera FPGA. The Core
is wrapped around with software drivers and examples for its ease of use and quick integration. The ready to use development board availability makes the integration faster. The core package also contains the reference design that can be used directly for starting a custom application development.
The core has been optimized for Altera FPGAs and its functionality has been verified on the hardware with Altera Quartus II. The package includes
ModelSim precompiled library for core simulation and verification.
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| Features |
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- Implementation of Link Layer & Protocol Layer
- Support 16-bit and 32-bit Phy layer data interface
- Supports CONTROL, BULK transfer without stream support
- USB2.0 backward compatible
- All Link layer power state handling
- Implements CRC calculation and generation in hardware
- Configurable end-point selection
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| Implementation Results |
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| IP Core |
Supported Families |
LEs/ALUTs |
Memory Bits |
| USB 3.0 Device (USB30SF) |
Cyclone III |
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| Stratix II |
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| Verification |
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- USB 3.0 Device IP core's functionality is verified in ModelSim simulation software using test bench written in Verilog HDL.
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| Deliverables |
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| Development Board |
- Cyclone III FPGA
- Texas USB1310 PHY
- 32MB SDRAM
- 8 MB FLASH
- USB 3.0 Standard B Connector
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Downloads
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