SD Host Controller IP Core FAQ

Pre-sales


1.	Does SLS SD Host Controller IP have SDIO interface?
2.	What type of SD card does your IP core supports?
3.	Does the core support DMA interface?
4.	Which mode does it supports for data communication?
5.	What is the cost of the IP core?
6.	What is the difference in OpenCore and Full version of IP core?
7.	What performance you have achieved using the IP Core?
8.	Can I get the source code of HAL?
9.	Do you provide source code of the IP core?
10.	Does it comply with SD host Controller V2.0?
11.	How do I verify core functionality in hardware as well as in simulation?
12.	I want a hardware only solution for my product. I do not intend to use Nios II processor or SOPC builder. Do you have a solution?
13.	Does the core support FPGA other than Altera?

IP Implementation

1.	Are DSP builder blocks provided for reading and writing to the SD card?
2.	Does the IO bank on the cyclone that interfaces with the SD Card have to run on 3.3V?
3.	Which SD clock frequency does it supports?
4.	How much block length does the IP core supports?

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Licensing/Installation

Answers

Pre-sales

1.	Does SLS SD Host Controller IP have SDIO interface?
	No. The IP core does not support SDIO interface but we can give SDIO interface as design services. Please contact info@slscorp.com.

2.	What type of SD card does your IP core supports?
	The IP core supports SD as well as SDHC Memory cards.

3.	Does the core support DMA interface?
	Yes, the core supports DMA interface. You can take a look at the setup reference design for implementing DMA in the system design.

4.	Which mode does it supports for data communication?
	The core supports SD 1-bit and 4-bit mode for data communication as per SD Physical Layer Specification v2.0.

5.	What is the cost of the IP core?
	For the cost of the IP core please contact info@slscorp.com.

6.	What is the difference in OpenCore and Full version of IP core?
	In the evaluation version of the IP core, you will be able to generate the time-limited programming file for the hardware which will expire after pre-defined time period. Once the program is downloaded and timeout occurs, the hardware evaluation IP Core will stop working. Initially, one (1) month evaluation license is provided which can be extended upon request and justification of the product evaluation needs. In full version of the IP core, you will be able to generate the programming file without timing limit.

7.	What performance you have achieved using the IP Core?
	190 Mbits/Sec in read and 160 Mbits/Sec in write speed achieved with SD Host controller IP core. (With Sandisk 4 GB Extream II Card).

8.	Can I get the source code of HAL?
	You will get the source code of HAL after registered yourself on SD organization.

9.	Do you provide source code of the IP core?
	The standard version of IP Core does not come with the source code but can be provided on request and payment of a separate license fee. However, some software applications ship with full source and are listed in the deliverables.

10.	Does it comply with SD host Controller V2.0?
	The IP core follows SD physical layer specification v2.0 and it supports high SD high capacity card.

11.	How do I verify core functionality in hardware as well as in simulation?
	The IP Core package includes an embedded evaluation demonstration board that can be used to verify the core functionality in hardware. The package does not contain any simulation library, but in future releases it may include it.

12.	I want a hardware only solution for my product. I do not intend to use Nios II processor or SOPC builder. Do you have a solution?
	No. it is not possible to use only core. You must have to use the SD host controller with the Nios II processor. But it may change as per the processor used in the design.

13.	Does the core support FPGA other than Altera?
	The package only supports Altera FPGA. If customer wants to implement it FPGA other than Altera then we can work mutually on design service agreement. For this please contact info@slscorp.com.

IP Implementation

1.	Are DSP builder blocks provided for reading and writing to the SD card?
	No, there is no DSP builder blocks provided, but we provide a ready to use reference design for using SD Card using our SD Host Controller IP Core (the core is required to be downloaded separately from the website).

2.	Does the IO bank on the cyclone that interfaces with the SD Card have to run on 3.3V?
	Any IO which are operates on 3.3 voltage level can be used for SD Card interface.

3.	Which SD clock frequency does it supports?
	The IP core supports variable clock frequency selection using software. By writing in to the register you can set the SD clock frequency.

4.	How much block length does the IP core supports?
	IP core supports up to variable block length to read/write to/from SD card. The block length is programmed by writing to BlockLength register in the software.