Short Term Course

A Short Term Course on VLSI (FPGA) Design

The course consists of 2 modules :

Regular Module (5 days)
Assignments Module

1. Regular Module:

Participants will have to attend the class for 5 days at the System Level Solutions Training Center located at Anand. Each day will consist of 8 hours. The day wise content is given below :

Day I:	Introduction to Programmable devices and the design flow

	Overview of ASICs and Programmable Devices Introduction to FPGA architecture Universal Design Methodology for programmable devices Make pre-project decisions to plan design Create, manage and compile Quartus II projects View compilation results

Day II:	Using Assignments and Settings in Quartus II software

	Make pre-project decisions to plan the design Plan and manage device I/O assignments using Pin Planner Assign clock and I/O constraints to improve design performance Analyze clock and input/output timing using TimeQuest

Day III:	Optimization and verification in Quartus II software

	Perform basic timing analysis with TimeQuest Create all required timing constraints (clock, I/O, multicycle, false paths) to fully constrain your FPGA Define physical region constraints for an FPGA design using LogicLock regions Manage user-defined design partitions using Quartus II incremental flow Apply incremental compilation to top-down & bottom-up design flows Debug designs in-system using the SignalTap II embedded logic analyzer Use external logic analyzer and pattern generator to debug designs

Day IV:	Designing a System on chip using SOPC builder and Nios II processor

	Configure & compile a Nios II design using SOPC Builder & Quartus II software Create software projects for the Nios II processor using Nios II IDE Compile, run, & debug embedded software Learn to access peripherals from C using the HAL API functions

Day V:	Do it yourself

	Create your own system and write a software for a customized project Solve your queries

2. Assignments Module:

Take home assignments are given for each day during the training. Participants are supposed to submit the assignments within the time frame given by the instructor in the regular module. Assignments are to be done at home and necessary software required will be given in the training kit provided on the first day.

Skills Required

Background in digital logic design
Ability to describe a hardware system using VHDL, Verilog or EDA schematic tool
Experience with PCs and the Windows operating system

Participants successfully completing the program and submitting the assignments on time will be presented with a certificate from SLS.

Fees

Registration fees: Rs. 500 (exclusive of program fees and non-refundable)
Program fees: Rs. 5000 (exclusive of food and accommodation)

Batches:

December 2008 (15th December to 19th December)
January 2009 (19th January to 23rd January)
February 2009 (16th February to 20th February)
March 2009 (16th March to 20th March)
April 2009 (13th April to 17th April)
May 2009 (18th May to 22nd May)