USB 2.0 Host Controller IP Core FAQ

Pre-sales


1.	What is the type of your Host?
2.	Do you have USB 2.0 Device IP Core?
3.	How many transfer types does IP core support?
4.	What performance you have achieved using the IP Core?
5.	Which platform does your IP core support?
6.	Do you provide the source code of your IP?
7.	Can I get the source code of the HAL?
8.	How do I verify core functionality in hardware as well as in simulation?

IP Implementation

1.	Does the core give simulation support?
2.	Does the core supports any type of USB device plug-in?
3.	Where does 60MHz clock come from in the IP core reference design?
4.	The maximum transfer rate we get is about 350Mbps. What should we expect to get with this part? What are the limiting factors?
5.	Does the core require external memory to store transmit or received data?

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Licensing/Installation

Answers

Pre-sales

1.	What is the type of your Host?
	The type of the Host Controller is an embedded.

2.	Do you have USB 2.0 Device IP Core?
	Yes, we do have different variants of USB 2.0 Device Controller IP core. You can find more information about the IP core from http://www.slscorp.com/pages/ipusb20sls.php

3.	How many transfer types does IP core support?
	The standard IP version is preconfigured for two (2) transfer types (Control and Bulk). Up to a total of four (4) transfer types are supported and may be added as per design requirements at additional cost.

4.	What performance you have achieved using the IP Core?
	352 Mbps in read and 356 Mbps in write speed achieved using DMA in USB 2.0 Host Controller IP core interfacing with Hi-Speed device. 8Mbps in read and write speed achieved using DMA in IP core interfacing with Full Speed device. The speed may vary as per the device.

5.	Which platform does your IP core support?
	The IP core can work on any of the platform windows, linux and uCLinux. SLS has developed the driver for each platform to work. In the standard package contains drivers for windows. For other platform, driver can be provided at additional cost.

6.	Do you provide the source code of your IP?
	Yes, we do provide source code of the IP core on additional cost. For that you can contact at info@slscorp.com.

7.	Can I get the source code of the HAL?
	Yes. You can request for the source code of HAL at info@slscorp.com at additional cost.

8.	How do I verify core functionality in hardware as well as in simulation?
	The IP Core package includes CoreCommander board that can be used to verify the core functionality in hardware. The package also includes a ModelSim precompiled library to simulate the design and verify basic transactions.

IP Implementation

1.	Does the core give simulation support?
	Yes the core gives support to do simulation. The package includes Altera ModelSim precompiled library for simulation using which you can verify the basic transaction of the core.

2.	Does the core supports any type of USB device plug-in?
	The IP core standard package supports only bulk transfer type. So with the standard package you can only detect bulk transfer supported device. For other transfer support, please contact info@slscorp.com.

3.	Where does 60MHz clock come from in the IP core reference design?
	In the reference design provided, the 60 MHz clock comes from the PHY chip. It is recommended to use the same clock for the PHY chip and the IP core to avoid synchronization issues

4.	The maximum transfer rate we get is about 350Mbps. What should we expect to get with this part? What are the limiting factors?
	The speed is depended on the Nios processor type, the cache size and DMA support. Please check your hardware design for the details. Also, it depends on the speed of the USB device you are using. The more speed will in turns high transfer rate.

5.	Does the core require external memory to store transmit or received data?
	The core is having on-chip dual port memory of 8 Kbytes. This memory is used to stored transmit and received data during communication with the device.