USB 2.0 Device, Software Enumeration FIFO Interface (USB20SF)
Model No. IPRUSB2SFP009
The USB 2.0 Device, Software Enumeration FIFO interface (USB20SF) IP Core is a FIFO based USB 2.0 device core with 32-bit Avalon/AXI interface and ULPI interface support. The core supports High Speed (480 Mbps), Full Speed (12 Mbps) and Low Speed (1.5 Mbps) functionality.
It has been designed to provide simplicity and flexibility along with its functionality has been verified on the hardware. Avalon/AXI interface allows to manage the control transfer using software, provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.
Block Diagram:
Features:
- Device controller specific features
- Supports LS (1.5 Mbps)*, FS (12 Mbps) and HS (480 Mbps) modes
- Supports Control, Bulk, Interrupt and Isochronous transfers
- Capable to support up to 31 endpoints (1 default control endpoint +15 IN/OUT endpoints)
- Supports software configurable endpoints
- Allows you to configure endpoints based on your needs
- Supports Suspend, Resume and Remote Wakeup features
- Supports Test modes (Test J, Test K, Test SE0 NAK, Test Packet)
- Supports UTMI + Low Pin interface (ULPI) interface
- The core has been optimized for popular FPGA devices and its functionality has been verified on the real hardware
- Ease of Use
- Ready to use component
- Software controlled CONTROL endpoint
- Simple FIFO interface to transfer data over non-control endpoint
*Low Speed (1.5 Mbps) support on Microchip/Xilinx platform is provided on special request, contact support@slscorp.com for more details.
FPGA Supported:
| FPGA | Supported Device Family |
|---|---|
| Intel | Cyclone 10, Cyclone V, Cyclone IV, Cyclone III Arria 10, Arria V, Arria II Stratix 10, Stratix V, Stratix IV, Stratix III Max 10 |
| Microchip | Polarfire |
| Xilinx | Ultrascale, Ultrascale+ |
Verification:
- USB20SF IP core's functionality is verified in ModelSim simulation software using test bench written in Verilog HDL
- The IP Core is tested with various USB 2.0 PHY Chip
Deliverables:
| Contents | Evaluation License | Full Development License |
|---|---|---|
| License Type | One (1) month evaluation license at no cost Note: License can be extended for another month after examining request (Evaluation Now) |
Encrypted IP Core Perpetual license for development Note: Other licensing schemes and source code are also available |
| Reference Design | Included for respective Development board | Included for respective development board |
| Demonstration | USB Read/Write | USB Read/Write |
| HAL Drivers | Yes | Yes |
| Sample Applications (with C code) | Enumeration | Enumeration |
| Encrypted IP Core design files with Control, 1-Bulk IN and 1-Bulk OUT endpoints | Yes | Yes |
| Drivers | Windows Reference Drivers (object code) | Windows Reference Drivers (object code) Note:Linux Driver available on request |
| Software Library (Compiled version) |
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| Technical Documents |
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| Programming files generation support | Time-limited (4 hours) | Full programming |
| Technical Support | Pre sales support from support team | 1 Year integration support |
Support:
- One year IP integration support available with the purchase of full version
- Additional support on chargeable basis for a period of 3 months or more
- IP Core modification support available at additional cost
Licensing:
- OpenCore Plus Evaluation : 1 month evaluation license at no cost
- Full : Project based Perpetual License
- Renewal : To continue support and getting future updates after a year of purchasing IP core, license renewal is available at nominal fees
Downloads:
| << Back to USB 2.0 | Go to USB20HR >> |
FAQs:
