Description
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The USB 2.0 Host Controller IP Core is a 32-bit Avalon interface compliant core and supports ULPI interface. It supports High Speed (HS), Full Speed (FS) and Low Speed (LS) modes.
IP core has been implemented in Verilog HDL and its functionality has been verified using different test cases in simulation environment as well as on hardware. It is provided as Altera Qsys Ready component and hence can be easily integrated in Qsys system.
Block Diagram:
Features:
- Supports Low Speed (1.5 Mbps), Full Speed (12 Mbps) and High Speed (480 Mbps) modes
- Supports Control, Bulk and Interrupt transfers
- Contains two different interface for Control Port and Data Port to improve Clock Domain Crossing (CDC) performance
- Supports Asynchronous Avalon clock interface
- Enables you to run Avalon interface (in turn Avalon Master - CPU) at clock frequency independent of ULPI bus
- Supports SPLIT transfer
- Optimized TD (Transfer Descriptor) structure
- Configurable memory depth
- Enables you to reduce resource utilization depending on application needs
- Supports UTMI + Low Pin interface (ULPI) interface
- Meets Altera Design Assistant guidelines
- Mass storage class speed performance
- Upto 14 MBPS speed for read operation
- Upto 11 MBPS speed for write operation
Implementation Results:
| Supported Family | Resource Utilization | Memory Blocks | Performance ( ULPI Clock - fmax ) |
|---|---|---|---|
| Cyclone III | 3070 LE | 16 M9K | 61MHz |
| Cyclone IV GX | 3070 LE | 16 M9K | 63MHz |
| Cyclone V | 1315 ALM | 16 M10K | 62MHz |
| Stratix III | 2060 ALUT | 1 M144K | 67MHz |
| Stratix IV | 2070 ALUT | 1 M144K | 66MHz |
| Stratix V | 1290 ALM | 8 M20K | 67MHz |
| Arria II | 2060 ALUT | 16 M9K | 64MHz |
| Arria V | 1305 ALM | 16 M10K | 63MHz |
| MAX 10 | 3070 LE | 16 M9K | 61MHz |
Verification:
- IP Core has been tested by interfacing it with USB 2.0 PHY (RN1133) on SLS HSIC development board.
- It has also been verified under simulation environment.
Deliverables:
| Contents | Evaluation License | Full Development License |
|---|---|---|
| License Type | One (1) month evaluation license at no cost Note: License can be extended for another month after examining request (Evaluation Now) |
Encrypted IP Core Perpetual license for development Note: Other licensing schemes and source code are also available |
| Reference Design | Included for SLS CoreCommander | Included for SLS CoreCommander |
| Demonstration | Mass Storage, Device Enumeration | Mass Storage, Device Enumeration |
| Nios II HAL Drivers | Included in Object Code | Included in Object code Note: Source Code available separately on request |
| Nios II Sample Applications (with C code) | Mass Storage, Device Enumeration | Mass Storage, Device Enumeration |
| Simulation Library | Altera Modelsim | Altera Modelsim |
| Technical Documents |
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| Technical Support | Pre sales support from support team | 1 Year integration support for Altera Quartus II |
Applications:
- Set-up Box
- Printer
- Television
- Music system
- Mass storage
Support:
- IP integration support available with the purchase of full version
- Additional support on chargeable basis for a period of 3 months or more
- IP Core modification support available at additional cost
Licensing:
- OpenCore Plus Evaluation : 1 month evaluation license at no cost
- Full : 1 Year development license with full version purchase for single project and single site
- Renewal : OpenCore Plus Evaluation license update at discounted price
Downloads:
| << Back to USB 2.0 |
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