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USB 3.0/3.1 Gen 1 Device, Software based enumeration FIFO Interface (USB30SF)

Model No. IPRUSB3SFP001

Rating: Not Rated Yet


This IP Core is now upgraded to eUSB 3.1 Gen 2 Device Controller (eUSB31SF) with backward compatibility, using FPGA in-built 10/5 Gbps transceiver. We recommend to use new version for new design. For detail, please visit eUSB 3.1 Gen 2 Device Controller (eUSB31SF)



The SLS USB 3.0/3.1 Gen 1 IP Core is the SuperSpeed core that supports connectivity between TI USB 3.0/3.1 Gen 1 PHY (TUSB1310 ) and Altera® FPGA. The IP Core is wrapped around with software drivers and examples for its ease of use and quick integration. The ready to use USB 3.0 development board availability makes the integration faster. The IP Core package also contains the reference design that can be used directly for starting a custom application development.

The IP Core has been optimized for Altera® FPGAs and its functionality has been verified on the hardware with Altera® Quartus II software. The package includes ModelSim precompiled library for IP Core simulation and verification.

Development Board:

  • Cyclone IV E FPGA
  • Texas USB1310 PHY
  • USB 2.0 to UART Port
  • 2x128 MB DDR2 SDRAM
  • 5x8 Gbit NAND FLASH
  • 64 Mbit SDR SDRAM
  • 64 Mbit CFI Flash
  • HSMC Connector
  • µSD Card Reader
  • GPIO Headers
  • 4xPush Button Switches and 4xLEDs
USB 3.0 Device

Actual Performance Data:

Although the SLS USB 3.0/3.1 Gen 1 IP Core is designed and proven working at maximum throughput in a point to point environment, in reality the overall systsem determines the real speed implementation would experience.

Notice: All Host Controllers are not cerated equally!!!

Block Diagram:


  • Implementation of Link Layer & Protocol Layer
  • Support 16-bit and 32-bit Phy layer data interface
  • Supports CONTROL, BULK transfer without stream support
  • USB2.0 backward compatible
  • All Link layer power state handling
  • Implements CRC calculation and generation in hardware
  • Configurable end-point selection

Implementation Results:

Supported FamilyResource UtilizationMemory BlocksPerformance ( Avalon Clock - fmax )
Cyclone IV10000 LE36 M9K250MHz
Cyclone V4710 ALM35 M10K405MHz
Stratix III5340 ALUT33 M9K730MHz
Stratix IV5215 ALUT33 M9k412MHz
Stratix V4797 ALM10 M20K717.36MHz
Arria II5497 ALM30 M9K700.28MHz
Arria V4703 ALM35 M10K338.41MHz
MAX 1010000 LE36 M9K250MHz


  • USB 3.0/3.1 Gen 1 IP core's functionality is verified in ModelSim simulation software using test bench written in Verilog HDL.


ContentsEvaluation LicenseFull Development License
License Type One (1) month evaluation license at no cost
Note: License can be extended for another month after examining request (Evaluation Now)
Encrypted IP Core Perpetual license for development
Note: Other licensing schemes and source code are also available
Reference Design Included for SLS USB3.0 board Included for SLS USB3.0 board
SLS USB3.0 Board Not included, need to purchase separately Included
  • USB Enumeration
  • USB Mass Storage Device Class
  • YUV2 Camera
  • USB Enumeration
  • USB Mass Storage Device Class
  • YUV2 Camera
Nios II Sample Applications (with C code) Enumeration Enumeration
Drivers Windows Reference Drivers (object code) Windows Reference Drivers (object code)
Software Library (Compiled version)
  • VC++
  • VC++
Simulation Library Altera ModelSim Altera ModelSim
Utilities USB View, Amcap and Enumeration Data Editor USB View, Amcap and Enumeration Data Editor
Technical Documents
  • IP Core User Guide
  • Window API User Guide
  • IP Core User Guide
  • Window API User Guide
Technical Support Pre sales support from support team 1 Year integration support for Altera Quartus II






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System Level Solutions Inc. 511 N. Washington Avenue,Marshall, Texas 75670. Ph: 001-408-852-0067