USB 3.0/3.1 Gen 1 Device
What can I do with the evaluation version of your core? How does this compare to the full production version?The evaluation version of the USB 3.0 IP Core is the OpenCore plus evaluation of this megafunction and it operates in tethered mode. This means that the downloaded program will remain inside the hardware for a particular amount of time only i.e. for 2 hours. Once the program is downloaded and timeout occurs, the hardware evaluation IP Core will stop working. Also, the OpenCore plus hardware evaluation feature adds additional logic to the design that may affect the timing and fitting of the design. Therefore, you can check whether the core meets your design requirements with the evaluation version with this time limited feature and then confidently go for full production version for your final product. Initially, one (1) month evaluation license is provided which can be extended upon request and justification of the product evaluation needs.
Do you provide the source code for your IP?Yes, we can provide the source code of the IP at additional price on request.
How many endpoints does the SLS USB 3.0 IP Core support?The USB 3.0 IP Core is preconfigured to support 3 endpoints - Control, Bulk In and Bulk Out. Additional endpoints are supported and can be added as per design requirements at additional cost.
Can I customize the vendor ID in the full version?Yes, you can customize the vendor ID in full as well as evaluation version of the IP Core. You can customize the value in "sls_usb.h" file provided in the IP Core setup.
How do I request the evaluation version of the core?You can request the evaluation version of the IP Core from http://www.slscorp.com/ip-cores/communication/usb-30-device.html page. Click on the request eval button on the top of the page. It asks you to sign in or register to send the request of IP Core and its evaluation license file.
How do I verify core functionality in hardware as well as in simulation?The IP Core package includes the USB 3.0 Development board (http://www.slscorp.com/products/development-boards/usb-3-0-development-board.html) that can be used to verify the functionality in hardware. The package also includes the ModelSim precompiled library to simulate the design and verify the basic transaction.
What is the maximum speed achieved with the core?The maximum speed achieved with the IP Core is ~1.5Gbps for Bulk Out transfer and ~2Gbps for Bulk In transfer.
How do I verify core functionality in hardware as well as in simulation?The SLS has developed a USB 3.0 board which provides all the accessibility to verify the USB 3.0 IP Core on hardware. The IP Core package includes a ModelSim precompiled library to simulate the design and verify basic transactions.
I run the demo file as per the instructions mentioned in the readme file, but I am still getting 'USB device not recognized' message. How can I solve this problem? Is there some problem with the files I downloaded?There is nothing wrong with the demo you downloaded on the board. After successfully downloading the .elf file, run the usbview utility to verify the USB device connection. If the device is not connected properly, you will see the message "Enumeration failed" and in such case you will find the message USB device not recognized. To solve this error, follow the steps below:
- Plug in one end of the 'b' type USB cable to the device and other end to the PC.
- Check that the USB cable complies with the specification and it is not faulty.
- Connect the USB cable to another USB port.
How can I configure the core to support a crystal input or external clock mode?Our IP core supports both crystal input and external clock input. For clock input, the IP Core has provided the reset_cnt.v file in which you have to set the xtal_remove and phy_xtal_sel_bit based on the clock input. The reference design for USB 3.0 development board uses the external clock input generated from IP Core. Based on the bit selection the clock is generated from the SDRAM_PLL and feed to the TI PHY chip.
Does u30_rx_elecIDLE bidirectional pin effect the input clock?No, u30_rx_elecIDLE bidirectional pin doesn't affect the clock input to TI-PHY.
What is the use of 'EP0 buffer 0 read used word' and 'EP0 buffer1 write used word'?'EP0 buffer0 read used word' - indicates number of bytes present in buffer 0 register. 'EP0 buffer1 write used word' - indicates number of bytes present in buffer 1 register.
How can you make a request UNSTALL?There is no need to clear stalled control endpoint from software. It will clear automatically when next set up packet interrupt is generated.
Can I read the register status for STALL in the EP0 disable register?EP0 disable register is a write only register and you cannot read the register status for STALL.
Can USB 3.0 development board operate at 500 MB/sec?As per the USB 3.0 IP Core specification, the maximum data transfer speed is 4.8 Gbps (500 MB/sec). But in actual the delay and overhead by the PHY, Link and Proto layers reduces the speed for data communication by ~1.5 Gbps. Also while communicating with the device we have to consider the overhead of the host controller as well. Hence it also reduces the speed at ~1.8 to 2 Gbps. By taking in account all these factors, we are able to achieve ~1.5 Gbps write and 2.5 Gbps read speed.
Do we need to have some external FIFO's to do just enumeration/receiving or sending small packages using EP0?No, need for external FIFO's for enumeration, receiving or sending small packaging data.
Is there any buffer/FIFO internally for EP0?Buffer memory is present for Endpoint 0 inside the core for IN and OUT data operation. Control Endpoint is handled by Nios II Controller.
What is the function of LINK_ERROR_REG?In this register due to the direct value of the current state assignment it generates a continuous interrupt to the software. Please refer USB 3.0 IP Core user guide for more information.