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Questions

  • Which type of documents do you provide in eUSB 3.1 Gen 2 IP Core Setup?

    We are providing user guides of the IP Core and HAL API. Along with each reference design, we are providing quick start document. Using it, user can easily extract and recompile the provided reference design at his/her end. Also, we are providing a document that helps user in creating project in Nios II Eclipse.
  • Which type of Host Controllers have been used to verify your eUSB 3.1 Gen 2 IP Core?

    eUSB 3.1 Gen 2 IP Core has been verified using ASMedia and Intel Gen 2 Host Controllers.
  • How much speed is achieved during raw read write data streaming?

    We have achieved around 7.2 Gbps speed during IN transfer and 7.5 Gbps during OUT transfer. Would you like to watch video? Please visit https://www.youtube.com/watch?v=w8WPzkID2_U.
  • How should we request evaluation package of your eUSB 3.1 Gen 2 IP Core?

  • Does eUSB 3.1 Gen 2 IP Core support Super Speed (Gen 1)?

    Yes, user can also use eUSB 3.1 Gen 2 IP Core in Gen 1 mode only.
  • Does eUSB 3.1 Gen 2 IP Core support High Speed (USB 2.0) mode?

    Yes, user can also use eUSB 3.1 Gen 2 IP Core in USB 2.0 mode only.
  • Does eUSB 3.1 Gen 2 IP Core use Intel's inbuilt transceiver for all modes (Super Speed Plus, Super Speed and USB 2.0)?

    No. eUSB 3.1 Gen 2 IP Core uses Intel's inbuilt transceiver for Gen 2 (Super Speed Plus) and Gen 1 (Super Speed) modes only. To use IP Core in USB 2.0 mode (High/Full/Low Speed), external PHY chip is needed.
  • Does eUSB 3.1 Gen 2 IP Core require external PHY chip?

    Yes. To use eUSB 3.1 Gen 2 IP Core in USB 2.0 mode, you will require external PHY. Following are the reasons why we need an external PHY chip for USB2.0. (1) USB requires both differential and single ended signalling. Certain bus states are indicated by single ended signals. For example, single ended zero (SE0) is used to perform USB reset operation. It is generated by holding both D+ and D- lines at low. During data transfer, it uses differential signaling.

    In order to get more idea, you are requested to refer section 7.1 Signalling from USB2.0 Specification. (2) It also uses some pull-up or pull-down registers. Either some pull-up registers or termination registers need to be attached or detached during run-time. For example, after speed negotiation, high speed device needs to enable high speed terminations on both D+/D- lines and needs to remove pull-up resistor from D+ lines.

  • Which external PHY chips does your eUSB 3.1 Gen 2 IP Core support?

    eUSB 3.1 Gen 2 IP Core (in USB 2.0 mode) supports any ULPI compliant PHY chips. It has been verified on Microchip's USB3320, USB3340, USB3300, Richnex's RN1133.
  • Which items are you providing in your eUSB 3.1 Gen 2 IP Core setup?

    • User Guide of IP Core and HAL API
    • Encrypted IP Core
    • Reference Designs
    • Ready made Demonstrations

  • Are you providing any reference design for evaluating your eUSB 3.1 Gen 2 IP Core?

    Yes, we have ready made reference designs available on below Development Kits for Quartus Prime Standard as well as Pro edition.

    • Arria 10 GX
    • Arria 10 SoC
    • Arria V GX
    • Cyclone 10 GX
    • Cyclone V GT

  • Which FPGA device falmilies do your eUSB 3.1 Gen 2 IP Core support?

    eUSB 3.1 Gen 2 IP Core supports Arria 10 and Cyclone 10 as of now. For Gen 1 mode, Arria V and Cyclone V are also supported by the IP Core.
  • Has eUSB 3.1 Gen 2 IP Core been verified on Cyclone 10 device falmily?

  • Are you providing reference design for Quartus Prime Pro?

    Yes. Please write us at This email address is being protected from spambots. You need JavaScript enabled to view it.
  • Can we use same reference design for all versions of Quartus?

    Yes. User can use same Quartus version or higher.
  • Does your eUSB 3.1 Gen 2 IP Core compliant?

    SLS IP core passes all TD6 and TD7 tests except following two test cases. Link Layer:

    1. TD6.2 : Skip Test (Fails for Gen2 Only). We will resolve this in next release of IP core.
    2. TD7.37 : Packet Pending Test (Fails for both Gen1 & Gen2)

    Electrical : Gen1 TX Electrical (LeCroyReport_Gen1 Tx 11090072_Run1.zip) : So far so good (except SSC). Gen2 TX Electrical (usbgen2_72_CP9_LeCroy--00001.zip) :  Due to some logical issue with Gen2 compliance pattern in IP core, we were not able to see run full TX compliance tests. However, we did get Eye opening parameter for CP9.

    In addition to this, Intel FPGA transceiver has following limitations:

    1. No support for SSC (Spread Spectrum Clock)
    2. No support for Far end receiver detection. (We are using Vbus signal from host to detect connect/disconnect event)

  • How many transfer types does your eUSB 3.1 Gen 2 IP Core support?

    As of now, Control and Bulk transfer types are supported. But in near future we are going to add support for Interrupt as well as Isochronous type. For more detail, write us at This email address is being protected from spambots. You need JavaScript enabled to view it.
  • Low Power mode support.

    We are not supporting the Low Power modes for Gen 2 and Gen 1.
  • Which interface does eUSB 3.1 Gen 2 IP Core support?

    As of now, eUSB 3.1 Gen 2 IP Core supports only Avalon interface for processor access. AXI 4 interface support is in development phase.
  • Do you have any ready to use demonstration?

    Yes. We have ready to use demonstration of streaming application using eUSB 3.1 Gen 2 IP Core for Arria/Cyclone 10 GX Development Kits.

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System Level Solutions Inc. 511 N. Washington Avenue,Marshall, Texas 75670. Ph: 001-408-852-0067