eUSB 3.1 Gen 2 Device Controller
Which type of documents do you provide in eUSB 3.1 Gen 2 IP Core Setup?We are providing user guides of the IP Core and HAL API. Along with each reference design, we are providing quick start document. Using it, user can easily extract and recompile the provided reference design at his/her end. Also, we are providing a document that helps user in creating project in Nios II Eclipse.
Which type of Host Controllers have been used to verify your eUSB 3.1 Gen 2 IP Core?eUSB 3.1 Gen 2 IP Core has been verified using ASMedia and Intel Gen 2 Host Controllers.
How much speed is achieved during raw read write data streaming?We have achieved around 7.2 Gbps speed during IN transfer and 8.6 Gbps during OUT transfer. Would you like to watch video? Please visit https://youtu.be/E3AQILLLwgc.
How should we request evaluation package of your eUSB 3.1 Gen 2 IP Core?For evaluation, please visit at https://www.slscorp.com/licensing/ip-licensing.html.
Which communication modes are supported by eUSB 3.1 Gen 2 IP core?eUSB 3.1 Gen2 IP core supports Gen 2 (Super Speed Plus), Gen 1 (Super Speed) as well as backward compatible with USB 2.0 mode. User can also use this IP core in USB 2.0 mode only.
Does eUSB 3.1 Gen 2 IP Core use FPGA's inbuilt transceiver for all modes (Super Speed Plus, Super Speed and USB 2.0)?eUSB 3.1 Gen 2 IP Core uses FPGA's inbuilt transceiver for Gen 2 (Super Speed Plus) and Gen 1 (Super Speed) modes only. To use IP Core in USB 2.0 mode (High/Full/Low Speed), external PHY chip is needed.
Does eUSB 3.1 Gen 2 IP Core require external PHY chip?To use eUSB 3.1 Gen 2 IP Core in USB 2.0 mode, you will require external PHY. Following are the reasons why we need an external PHY chip for USB2.0. (1) USB requires both differential and single ended signalling. Certain bus states are indicated by single ended signals. For example, single ended zero (SE0) is used to perform USB reset operation. It is generated by holding both D+ and D- lines at low. During data transfer, it uses differential signaling.
In order to get more idea, you are requested to refer section 7.1 Signalling from USB2.0 Specification. (2) It also uses some pull-up or pull-down registers. Either some pull-up registers or termination registers need to be attached or detached during run-time. For example, after speed negotiation, high speed device needs to enable high speed terminations on both D+/D- lines and needs to remove pull-up resistor from D+ lines.
Which external PHY chips does your eUSB 3.1 Gen 2 IP Core support?eUSB 3.1 Gen 2 IP Core (in USB 2.0 mode) supports any ULPI compliant PHY chips. It has been verified on Microchip's USB3320, USB3340, USB3300, Richnex's RN1133.
Which items are you providing in your eUSB 3.1 Gen 2 IP Core setup?
- User Guide of IP Core and HAL API
- Encrypted IP Core
- Reference Designs
- Ready to use Demonstrations
Are you providing any reference design for evaluating your eUSB 3.1 Gen 2 IP Core?Yes, we provide reference design for respective Development Board and eUSB 3.1 FMC Snap On Board.
Which FPGA device falmilies do your eUSB 3.1 Gen 2 IP Core support?
FPGA Supported Device Family Intel
Gen 2 mode with backward compatibility: Stratix10, Arria10, Cyclone10
Gen 1 mode with backward compatibility: Cyclone V, Arria V, Stratix V
Microchip Gen 2 mode with backward compatibility: Polarfire
Can we use same reference design for all versions of Quartus/Libero?Yes. User can use same Quartus/Libero version or higher.
Low Power mode support.We are not supporting the Low Power modes for Gen 2 and Gen 1.
Which interface does eUSB 3.1 Gen 2 IP Core support?eUSB 3.1 Gen 2 IP Core supports Avalon as well as AXI 4 interface.
Do you have any ready to use demonstration?Yes. We have ready to use demonstration of streaming application as well as Loopback test. eUSB 3.1 Gen 2 IP Core demonstration for Mass Storage and UVC will be provided based on request.
Don’t want to use NIOS. Explain use of NIOS in IP core.Use of NIOS processor is to manage the communication for control EP (EP0) only. For non-zero endpoint, you need to write your own RTL logic. Footprint of NIOS code is small and can fit into FPGA onchip RAM. We do provide ready to use NIOS HAL source with IP core to minimize user's efforts.
Does the IP support LFPS?Yes. IP Supports LFPS. Although IntelFPGA transceiver does not support RX Electrical idle, IP core uses glue logic to detect LFPS.
Does this IP core for USB 3.2 (20Gbps)?As of now it support USB 3.2 Gen2x1 (10Gbps).